參數(shù)資料
型號(hào)： DS3106LN+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 15/92頁(yè)
文件大?。?/td> 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時(shí)卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 1429 (CN2011-ZH PDF)
DS3106
22
7.7.1.3 Locked State
The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states
when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.5). In the locked state
the output clocks track the phase and frequency of the selected reference.
If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the locked state.
While in the locked state, if the selected reference becomes inactive and an activity alarm is raised (corresponding
ACT bit set in the ISR2 register), the selected reference is marked invalid (ICn bit goes low in the VALSR1
register), and the LOS pin is asserted. If the input stays inactive for 2 seconds, the state machine transitions to the
holdover state. If the DPLL is switched to the other input and that input is active, the state machine transitions to
the prelocked 2 state.
7.7.1.4 Loss-of-Lock State
When the loss-of-lock detectors (see Section 7.7.5) indicate loss-of-phase lock, the state machine immediately
transitions from the locked state to the loss-of-lock state. If phase lock is regained during that period for more than
2 seconds while in the loss-of-lock state, the state machine transitions back to the locked state.
While in the loss-of-lock state, if the selected reference is becomes inactive, an activity alarm is raised
(corresponding ACT bit set in the ISR2 register), the selected reference is marked invalid (ICn bit goes low in the
VALSR1 register), and the LOS pin is asserted. If the input stays inactive for 2 seconds, the state machine
transitions to the holdover state. If the DPLL is switched to the other input and that input is active, the state
machine transitions to the prelocked 2 state.
7.7.1.5 Prelocked 2 State
The prelocked and prelocked 2 states are similar. If phase lock (see Section 7.7.5) is achieved for more than 2
seconds, the state machine transitions to locked mode. While in the prelocked 2 state, if the selected reference is
becomes inactive, an activity alarm is raised (corresponding ACT bit set in the ISR2 register), the selected
reference is marked invalid (ICn bit goes low in the VALSR1 register), and the LOS pin is asserted. If the input
stays inactive for 2 seconds, the state machine transitions to the holdover state.
7.7.1.6 Holdover State
The device reaches the holdover state when it declares its selected reference invalid for 2 seconds. During
holdover the T0 DPLL is not phase-locked to any input clock but instead generates its output frequency based on
previous frequencies while it was locked. When the selected reference becomes active, the state machine
immediately transitions from holdover to the prelocked 2 state, and tries to lock to the selected reference.
7.7.1.6.1Automatic Holdover
For automatic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or
averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the DPLL’s current
frequency 50ms to 100ms before entry into holdover (i.e., the value of the FREQ field in the FREQ1, FREQ2, and
FREQ3 registers). The FREQ field is the DPLL’s integral path and, therefore, is an average frequency with a rate of
change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not used in order to
minimize the effect of recent phase disturbances on the holdover frequency.
In averaged mode (AVG = 1 in HOCR3 and FRUNHO = 1 in MCR3), the holdover frequency is set to an internally
averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged over a
one-second period. The T0 DPLL indicates that it has acquired a valid holdover value by setting the HORDY status
bit in MSR4 (latched status). If the T0 DPLL must enter holdover before the one-second average is available, an
instantaneous value 50ms to 100ms old from the integral path is used instead.
7.7.1.6.2Free-Run Holdover
For free-run holdover (FRUNHO = 1 in MCR3), the output frequency accuracy is generated with the accuracy of
the external oscillator frequency. The actual frequency is the frequency of the external oscillator plus the value of
the MCLK offset specified in the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). When
MCR3.FRUNHO is set the HOCR3:AVG bit is ignored.
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