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參數(shù)資料
型號: DS26324GN+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 5/120頁
文件大小: 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 帶卷 (TR)
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
102 of 120
Table 9-4. Intel Write Cycle Characteristics
(VDD = 3.3V ±5%, TJ = -40°C to +125°C.) (Note 1) (See Figure 9-3 and Figure 9-4.)
SIGNAL
NAME(S)
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
NOTES
WRB
t1
Pulse width
40
ns
2
CSB
t2
Setup time to WRB
0
ns
2
CSB
t3
Hold time to WRB
0
ns
2
AD[7:0]
t4
Setup time to ALE
2
ns
2
A[5:0]
t5
Hold time from WRB
0
ns
2
D[7:0], AD[7:0]
t6
Input setup time to WRB
10
ns
2
D[7:0], AD[7:0]
t7
Input hold time to WRB
5
ns
2
RDYB
t8
Enable delay from CSB active
20
ns
2
RDYB
t9
Delay time from WRB active
10
ns
2
RDYB
t10
Delay time from WRB inactive
0
ns
2
RDYB
t11
Disable delay time from CSB inactive
15
ns
2
ALE
t12
Pulse width
5
ns
2
AD[7:0]
t13
Hold time from ALE inactive
3
ns
2
A[5:0]
t14
Valid address to WRB inactive
35
ns
2
Note 1:
The timing parameters in this table are guaranteed by design (GBD).
Note 2:
The input/output timing reference level for all signals is VDD/2.
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