參數(shù)資料
型號: DS26324GN+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 112/120頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 帶卷 (TR)
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
91 of 120
7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS26324 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26324 contains the
following as required by IEEE 1149.1 Standard Test-Access Port and Boundary-Scan Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE
1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins: TRSTB, TCLK,
TMS,
TDI,
and
TDO.
See
the
pin
descriptions
for
details.
For
the
latest
BSDL
files
go to www.maxim-ic.com/tools/bsdl/ and search for DS26324.
Figure 7-1. JTAG Functional Block Diagram
+V
BOUNDARY SCAN
REGISTER
INDENTIFICATION
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
TDI
TMS
TCLK
TRSTB
TDO
+V
TEST ACCESS PORT
CONTROLLER
MUX
10k
10k
10k
SELECT
OUTPUT ENABLE
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