參數(shù)資料
型號: DS26324GN+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 105/120頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應(yīng)商設(shè)備封裝: 256-CSBGA(17x17)
包裝: 帶卷 (TR)
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
85 of 120
Register Name:
BPCR1
Register Description:
BERT Pattern Configuration Register 1
Register Address (LIUs 1–8):
02h
Register Address (LIUs 9–16):
22h
Bit #
7
6
5
4
3
2
1
0
Name
QRSS
PTS
PLF4
PLF3
PLF2
PLF1
PLF0
Default
0
Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
20 + x17 + 1. The output of the pattern generator will be forced to one if the next fourteen
output bits are all zero.
Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). These five bits control the “l(fā)ength” feedback of the pattern
generator. The “l(fā)ength” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name:
BPCR2
Register Description:
BERT Pattern Configuration Register 2
Register Address (LIUs 1–8):
03h
Register Address (LIUs 9–16):
23h
Bit #
7
6
5
4
3
2
1
0
Name
PTF4
PTF3
PTF2
PTF1
PTF0
Default
0
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
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