參數(shù)資料
型號: DS26324GN+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 2/120頁
文件大?。?/td> 0K
描述: IC LIU E1/T1/J1 3.3V 256-CSBGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 500
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 16/16
規(guī)程: LIN
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA,CSBGA
供應商設備封裝: 256-CSBGA(17x17)
包裝: 帶卷 (TR)
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
10 of 120
4 PIN DESCRIPTION
Table 4-1. Pin Descriptions
NAME
PIN
TYPE
FUNCTION
ANALOG TRANSMIT AND RECEIVE
TTIP1
E1
Analog
output
Transmit Bipolar Tip for Channels 1–16. These pins are differential
line driver tip outputs. These pins can be high impedance if pin OE is
low. When “1” is set in the Output Enable Register OE bit, the
associated TTIPn pin will be enabled when the OE pin is high. The
differential outputs of TTIPn and TRINGn can provide internal
matched impedance for E1 75
, E1 120, T1 100, or J1 110.
If the TCLK input for a given LIU is held low for 64 MCLKs, that LIU’s
transmitter is powered down and the TTIP/TRING outputs are high
impedance.
TTIP2
F1
TTIP3
K1
TTIP4
L1
TTIP5
T5
TTIP6
T6
TTIP7
T10
TTIP8
T11
TTIP9
M16
TTIP10
L16
TTIP11
G16
TTIP12
F16
TTIP13
A12
TTIP14
A11
TTIP15
A7
TTIP16
A6
TRING1
E2
Analog
output
Transmit Bipolar Ring for Channels 1–16. These pins are
differential line driver ring outputs. These pins can be high impedance
if pin OE is low. When “1” is set in the Output Enable Register OE bit,
the associated TRINGn pin will be enabled when the OE pin is high.
The differential outputs of TTIPn and TRINGn can provide internal
matched impedance for E1 75
, E1 120, T1 100, or J1 110.
If the TCLK input for a given LIU is held low for 64 MCLKs, that LIU’s
transmitter is powered down and the TTIP/TRING outputs are high
impedance.
TRING2
F2
TRING3
K2
TRING4
L2
TRING5
R5
TRING6
R6
TRING7
R10
TRING8
R11
TRING9
M15
TRING10
L15
TRING11
G15
TRING12
F15
TRING13
B12
TRING14
B11
TRING15
B7
TRING16
B6
RTIP1
A1
Analog
input
Receive Bipolar Tip for Channels 1–16. Receive analog input for
differential receiver. Data and clock are recovered and output at
RPOS/RNEG and RCLK pins, respectively. The differential inputs of
RTIPn and RRINGn can provide internal impedance matching with
external resistance for E1 75
, E1 120, T1 100, or J1 110.
RTIP2
C1
RTIP3
H1
RTIP4
N1
RTIP5
T1
RTIP6
T3
RTIP7
T8
RTIP8
T13
RTIP9
T16
RTIP10
P16
RTIP11
J16
RTIP12
D16
RTIP13
A16
RTIP14
A14
RTIP15
A9
RTIP16
A4
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