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參數(shù)資料
| 型號： | DS26303LN-75+A3 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 37/101頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E1/T1/J1 3.3V 144-ELQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP 裸露焊盤 |
| 包裝： | 托盤 |
| 其它名稱： | 90-26303+7N3 |
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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
40 of 101
5.1.3
Individual LIU Registers
Register Name:
IJAE
Register Description:
Individual Jitter Attenuator Enable Register
Register Address:
00h
Bit #
7
6
5
4
3
2
1
0
Name
IJAE8
IJAE7
IJAE6
IJAE5
IJAE4
IJAE3
IJAE2
IJAE1
Default
0
Bits 7 to 0: Individual Jitter Attenuator Enable Channel n (IJAEn).
When this bit is set, the LIUn jitter attenuator
is enabled. Note that if the GC.JAE bit is set, this register is ignored.
Register Name:
IJAPS
Register Description:
Individual Jitter Attenuator Position Select Register
Register Address:
01h
Bit #
7
6
5
4
3
2
1
0
Name
IJAPS8
IJAPS7
IJAPS6
IJAPS5
IJAPS4
IJAPS3
IJAPS2
IJAPS1
Default
0
Bits 7 to 0: Individual Jitter Attenuator Position Select Channel n (IJAPSn).
When this bit is set , the jitter
attenuator is in the receive path of LIUn, and when this bit is reset the jitter attenuator is in the transmit path of
LIUn. Note that if the GC.JAE bit is set, this register is ignored.
Register Name:
IJAFDS
Register Description:
Individual Jitter Attenuator FIFO Depth Select Register
Register Address:
02h
Bit #
7
6
5
4
3
2
1
0
Name
IJAFDS8
IJAFDS7
IJAFDS6
IJAFDS5
IJAFDS4
IJAFDS3
IJAFDS2
IJAFDS1
Default
0
Bits 7 to 0: Individual Jitter Attenuator FIFO Depth Select n (IJAFDSn).
When this bit is set for LIUn, the jitter
attenuator FIFO depth is 128 bits. When reset, the jitter attenuator FIFO depth is 32 bits. Note that if the
GC.IJAFDS bit is set, this register is ignored.
Register Name:
IJAFLT
Register Description:
Individual Jitter Attenuator FIFO Limit Trip Register
Register Address:
03h
Bit #
7
6
5
4
3
2
1
0
Name
IJAFLT8
IJAFLT7
IJAFLT6
IJAFLT5
IJAFLT4
IJAFLT3
IJAFLT2
IJAFLT1
Default
0
Bits 7 to 0: Individual Jitter Attenuator FIFO Limit Trip n (IJAFLTn).
Set when the jitter attenuator FIFO
reaches to within 4 bits of its useful limit for the transmitter of LIUn. This bit is cleared when read if GISC.CWE is
reset. This bit is cleared by a write operation to the bit if GISC.CWE is set.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26303LN-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303LN-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26-32.768-STD-020 | 制造商:Micro Crystal Switzerland 功能描述: |
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