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參數(shù)資料
| 型號： | DS26303LN-75+A3 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 30/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1/T1/J1 3.3V 144-ELQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP 裸露焊盤 |
| 供應商設(shè)備封裝： | 144-LQFP 裸露焊盤 |
| 包裝： | 托盤 |
| 其它名稱： | 90-26303+7N3 |
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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
34 of 101
Register Name:
ATAOS
Register Description:
Automatic Transmit All-Ones Select Register
Register Address:
0Eh
Bit #
7
6
5
4
3
2
1
0
Name
ATAOS8
ATAOS7
ATAOS6
ATAOS5
ATAOS4
ATAOS3
ATAOS2
ATAOS1
Default
0
Bit 7 to 0: Automatic Transmit All-Ones Select Channel n (ATAOSn).
When this bit is set an all-ones signal is
sent if a loss of signal is detected for LIUn. The all-ones signal uses MCLK as the reference clock.
Register Name:
GC
Register Description:
Global Configuration Register
Register Address:
0Fh
Bit #
7
6
5
4
3
2
1
0
Name
RIMPMS
AISEL
SCPD
CODE
JADS
—
JAPS
JAE
Default
0
Bit 7: Receive Impedance Mode Select (RIMPMS).
When this bit is set, the internal impedance mode is selected,
so all receive lines (RTIPn and RINGn) require no external resistance component. When this mode is selected, the
die-attach pad on the bottom of the package should be connected to ground for thermal dissipation. When reset,
external impedance mode is selected so all receive lines (RTIPn and RINGn) require external resistance. Note that
when in external impedance mode, if TS.RIMPOFF is reset, the resistance is still adjusted internally for the T1
(100
Ω), J1 (110Ω), and E1(75Ω) modes of operation by the template selected so that only one resistor value is
required externally. In E1 (120
Ω), external impedance mode has no need for any internal adjustment.
Bit 6: AIS Enable During Loss (AISEL).
When this bit is set, for all channels, an AIS is sent to the system side
upon detecting an LOS on the corresponding channel. The individual settings in the IAISEL register are ignored
when this bit is set. When reset, the IAISEL register has control.
Bit 5: Short-Circuit-Protection Disable (SCPD).
If this bit is set, the short-circuit protection is disabled for all the
transmitters. The individual settings in ISCPD are ignored when this bit is set. When reset, the ISCPD register has
control.
Bit 4: Code (CODE).
If this bit is set, AMI encoding/decoding is selected. The individual settings in register LCS
are ignored when this bit is set. If reset, the LCS register has control.
Bit 3: Jitter Attenuator Depth Select (JADS).
If this bit is set the jitter attenuator FIFO depth is 128 bits. The
individual settings in register IJAFDS are ignored if this bit is set. If reset, the IJAFDS register has control.
Bit 1: Jitter Attenuator Position Select (JAPS).
When the JAPS bit is set high, the jitter attenuator is in the
receive path, and when it is set low, it is in the transmit path. The individual settings in register IJAPS are ignored if
this bit is set. If reset, the IJAPS register has control.
Bit 0: Jitter Attenuator Enable (JAE).
When this bit is set the jitter attenuator is enabled. The individual settings in
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26303LN-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303LN-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-XXX+ | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26-32.768-STD-020 | 制造商:Micro Crystal Switzerland 功能描述: |
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