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參數(shù)資料
| 型號： | DS2404B |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/29頁 |
| 文件大小： | 0K |
| 描述： | IC ECONORAM TIMECHIP 5.5V 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 77 |
| 系列： | EconoRAM |
| 類型： | 二進(jìn)制計數(shù)器 |
| 特點(diǎn)： | 警報器，方波輸出 |
| 時間格式： | 二進(jìn)制 |
| 數(shù)據(jù)格式： | 二進(jìn)制 |
| 接口： | 1 線和 3 線 |
| 電源電壓： | 2.8 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
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DS2404
17 of 29
1-WIRE SIGNALING
The DS2404 requires strict protocols to ensure data integrity. The protocol consists of five types of
signaling on one line: Reset Sequence with reset pulse and presence pulse, write 0, write 1, Read Data
and interrupt pulse. All these signals except presence pulse and interrupt pulse are initiated by the bus
master.
The initialization sequence required to begin any communication with the DS2404 is shown in Figure 10.
A reset pulse followed by a presence pulse indicates the DS2404 is ready to send or receive data given the
correct ROM command and memory function command.
The bus master transmits (TX ) a reset pulse (tRSTL , minimum of 480 μs). The bus master then releases the
line and goes into receive mode (RX ). The 1-Wire bus is pulled to a high state via the pull-up resistor.
After detecting the rising edge on the date line, the DS2404 waits (tPDH , 15-60 μs) and then transmits the
presence pulse (tPDL, 60 - 240 μs). There are special conditions if interrupts are enabled where the bus
master must check the state of the 1-Wire bus after being in the RX mode for 480 μs. These conditions
will be discussed in the “Interrupt” section.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2404 to the master
by triggering a delay circuit in the DS2404. During write time slots, the delay circuit determines when the
DS2404 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2404 will hold the data line low overriding the 1 generated by the master. If
the data bit is a “1”, the device will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10
480
μs ≤ tRSTL < ∞ *
480
μs ≤ tRSTH < ∞ (includes recovery time)
15
μs ≤ tPDH < 60 μs
60
μs ≤ tPDL < 240 μs
In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always
be less than 960
μs.
RESISTOR
MASTER
DS2404
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| DS2415P+T&R | IC TIME CHIP 1-WIRE 6-TSOC |
| DS2417X/T&R | IC TIMECHIP W/INTRPT 1WIRE CSP |
| DS26502LN+ | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2404B/T&R | 制造商:Maxim Integrated Products 功能描述:ECONORAM/TIME, SSOP16-TRL (GENERIC) - Tape and Reel |
| DS2404B+ | 制造商:Maxim Integrated Products 功能描述:REAL TIME CLOCK SERL 512BYTE 16SSOP - Rail/Tube |
| DS2404B+T&R | 制造商:Maxim Integrated Products 功能描述:REAL TIME CLOCK SERL 512BYTE 16SSOP - Tape and Reel |
| DS2404FP000 | 制造商:Thomas & Betts 功能描述:200A,CON,3P4W,MG,404,3P480V |
| DS2404FP000/DF2029 | 制造商:Thomas & Betts 功能描述:RS DS2404FP000/DF2029 200A,CON,3P4W |
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