The 3–wire bus is comprised of three signals. The" />
參數(shù)資料
型號: DS2404B
廠商: Maxim Integrated Products
文件頁數(shù): 14/29頁
文件大?。?/td> 0K
描述: IC ECONORAM TIMECHIP 5.5V 16SSOP
標準包裝: 77
系列: EconoRAM
類型: 二進制計數(shù)器
特點: 警報器,方波輸出
時間格式: 二進制
數(shù)據(jù)格式: 二進制
接口: 1 線和 3 線
電源電壓: 2.8 V ~ 5.5 V
電壓 - 電源,電池: 2.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
DS2404
21 of 29
TYPE 2 INTERRUPT (SPECIAL CASE) Figure 15
3-WIRE I/O COMMUNICATIONS
The 3–wire bus is comprised of three signals. These are the RST (reset) signal, the CLK (clock) signal,
and the DQ (data) signal. All data transfers are initiated by driving the RST input high. Driving the RST
input low terminates communication. (See Figures 19 and 20.)
A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, the data must be
valid during the rising edge of a clock cycle. Command bits and data bits are input on the rising edge of
the clock and data bits are output on the falling edge of the clock. When reading data from the DS2404,
the DQ pin goes to a high impedance state while the clock is high. Taking RST low will terminate any
communication and cause the DQ pin to go to a high impedance state.
POWER CONTROL
There are two methods of supplying power to the DS2404, VCC Operate mode with battery backup and
Battery Operate mode. If the DS2404 is used in an application where battery backup is not desired, the
part must be wired for Battery Operate mode.
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