參數(shù)資料
型號: DS2404B
廠商: Maxim Integrated Products
文件頁數(shù): 27/29頁
文件大?。?/td> 0K
描述: IC ECONORAM TIMECHIP 5.5V 16SSOP
標(biāo)準(zhǔn)包裝: 77
系列: EconoRAM
類型: 二進制計數(shù)器
特點: 警報器,方波輸出
時間格式: 二進制
數(shù)據(jù)格式: 二進制
接口: 1 線和 3 線
電源電壓: 2.8 V ~ 5.5 V
電壓 - 電源,電池: 2.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 管件
DS2404
7 of 29
Alarm Registers
The alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same
manner. When the value of a given counter equals the value in its associated alarm register, the
appropriate flag bit is set in the status register. If the corresponding interrupt enable bit(s) in the status
register is set, an interrupt is generated. If a counter and its associated alarm register are write protected
when an alarm occurs, access to the device becomes limited. (See “Status/Control”, “Interrupts”, and the
“Programmable Expiration” sections.)
STATUS/CONTROL REGISTERS
The status and control registers are the first two bytes of page 16 (see “Memory Map”, Figure 4).
Status Register
7
6
5
4
3
2
1
0
X
CCE
ITE
RTE
CCF
ITF
RTF
0200h
0
RTF
Real-time clock alarm flag
1
ITF
Interval timer alarm flag
2
CCF
Cycle counter alarm flag
When a given alarm occurs, the corresponding alarm flag is set to a logic 1. The alarm flag(s) is cleared
by reading the status register.
3
RTE
Real-time interrupt enable
4
ITE
Interval timer interrupt enable
5
CCE
Cycle counter interrupt enable
Writing any of the interrupt enable bits to a logic 0 will allow an interrupt condition to be generated when
its corresponding alarm flag is set (see “Interrupts” section).
Control Register
7
6
5
4
3
2
1
0
DSEL
START
STOP
MAN.
AUTO
OSC
RO
WPC
WPI
WPR
0201h
0
WPR Write protect real-time clock/alarm registers
1
WPI
Write protect interval timer/alarm registers
2
WPC Write protect cycle counter/alarm registers
Don’t care bits
Read Only
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