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| 型號(hào)： | DS21FT44N |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA300 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300 |
| 文件頁數(shù)： | 87/117頁 |
| 文件大?。?/td> | 691K |
| 代理商： | DS21FT44N |
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DS21FT44/DS21FF44
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Table 19-1. HDLC CONTROLLER REGISTER LIST
NAME
FUNCTION
HDLC Control Register (HCR)
General control over the HDLC controller
HDLC Status Register (HSR)
Key status information for both transmit and receive
directions
HDLC Interrupt Mask Register (HIMR)
Allows/stops status bits to/from causing an interrupt
Receive HDLC Information Register
(RHIR)
Status information on receive HDLC controller
Receive HDLC FIFO Register (RHFR)
Access to 64-byte HDLC FIFO in receive direction
Receive HDLC DS0 Control Register 1
(RDC1)
Receive HDLC DS0 Control Register 2
(RDC2)
Controls the HDLC function when used on DS0 channels
Transmit HDLC Information Register
(THIR)
Status information on transmit HDLC controller
Transmit HDLC FIFO Register (THFR)
Access to 64–byte HDLC FIFO in transmit direction
Transmit HDLC DS0 Control Register 1
(TDC1)
Transmit HDLC DS0 Control Register 2
(TDC2)
Controls the HDLC function when used on DS0 channels
19.2. HDLC Status Registers
Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a
particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be
set to a one. Some of the bits in these three status registers are latched and some are real time bits that are
not latched. Section 19.4 contains register descriptions that list which bits are latched and which are not.
With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred
again. The real time bits report the current instantaneous conditions that are occurring and the history of
these bits is not latched.
Like the other status registers in the framer, the user will always proceed a read of any of the three
registers with a write. The byte written to the register will inform the framer which of the latched bits the
user wishes to read and have cleared (the real time bits are not affected by writing to the status register).
The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read
and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with current value and it will be cleared. When a
zero is written to a bit position, the read register will not be updated and the previous value will be held.
A write to the status and information registers will be immediately followed by a read of the same
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21FT44N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q348 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q348B | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q348DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS21Q348N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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