參數(shù)資料
型號(hào): DS21FT44N
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁數(shù): 45/117頁
文件大小: 691K
代理商: DS21FT44N
DS21FT44/DS21FF44
33 of 117
IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex)
(MSB)
(LSB)
T1E1
0
ID3
ID2
ID1
ID0
SYMBOL
POSITION
NAME AND DESCRIPTION
T1E1
IDR.7
T1 or E1 Chip Determination Bit
0 = T1 chip
1 = E1 chip
ID3
IDR.3
Chip Revision Bit 3. MSB of a decimal code that represents
the chip revision.
ID2
IDR.1
Chip Revision Bit 2
ID1
IDR.2
Chip Revision Bit 1
ID0
IDR.0
Chip Revision Bit 0. LSB of a decimal code that represents
the chip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address = 10 Hex)
(MSB)
(LSB)
RSMF
RSM
RSIO
FRC
SYNCE
RESYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
RSMF
RCR1.7
RSYNC Multiframe Function. Only used if the RSYNC pin
is programmed in the multiframe mode (RCR1.6 = 1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSM
RCR1.6
RSYNC Mode Select
0 = frame mode (See timing diagrams in Section 22.)
1 = multiframe mode (See timing diagrams in Section 22.)
RSIO
RCR1.5
RSYNC I/O Select. (Note: this bit must be set to zero when
RCR2.1 = 0).
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled)
RCR1.4
Not Assigned. Should be set to zero when written.
RCR1.3
Not Assigned. Should be set to zero when written.
FRC
RCR1.2
Frame Resync Criteria
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error
three consecutive times
SYNCE
RCR1.1
Sync Enable
0 = auto resync enabled
1 = auto resync disabled
RESYNC
RCR1.0
Resync. When toggled from low to high, a resync is initiated.
Must be cleared and set again for a subsequent resync.
相關(guān)PDF資料
PDF描述
DS21FT44 DATACOM, FRAMER, PBGA300
DS21Q352 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
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DS21Q42TN DATACOM, FRAMER, PQFP128
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