參數(shù)資料
型號: DS21FT44N
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁數(shù): 51/117頁
文件大小: 691K
代理商: DS21FT44N
DS21FT44/DS21FF44
39 of 117
constant Remote Alarm will be transmitted if the framer cannot find CRC4 multiframe synchronization
within 400ms as per G.706.
It is an illegal state to have both CCR2.4 and CCR2.5 set to one at the same time.
CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
RSRE
THSE
TBCS
RCLA
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR3.7
Transmit Side Elastic Store Enable
0 = elastic store is bypassed
1 = elastic store is enabled
TCBFS
CCR3.6
Transmit Channel Blocking Registers (TCBR) Function
Select
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
TIRFS
CCR3.5
Transmit Idle Registers (TIR) Function Select. See Section
15 for details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
(i.e., Per Channel Loopback function)
CCR3.4
Not Assigned. Should be set to zero when written.
RSRE
CCR3.3
Receive Side Signaling Reinsertion Enable. See Section 14
for details.
0 = do not reinsert signaling bits into the data stream presented
at the RSER pin
1 = reinsert the signaling bits into data stream presented at the
RSER pin
THSE
CCR3.2
Transmit Side Hardware Signaling Insertion Enable. See
Section 14 for details.
0 = do not insert signaling from the TSIG pin into the data
stream presented at the TSER pin
1 = insert signaling from the TSIG pin into the data stream
presented at the TSER pin
TBCS
CCR3.1
Transmit Side Backplane Clock Select
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048MHz
RCLA
CCR3.0
Receive Carrier Loss (RCL) Alternate Criteria
0 = RCL declared upon 255 consecutive zeros (125s)
1 = RCL declared upon 2048 consecutive zeros (1ms)
相關(guān)PDF資料
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DS21FT44 DATACOM, FRAMER, PBGA300
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DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
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