參數(shù)資料
型號: DS21FT44N
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁數(shù): 66/117頁
文件大?。?/td> 691K
代理商: DS21FT44N
DS21FT44/DS21FF44
52 of 117
E-Bit Counter
E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E-bit is set to zero. Since the maximum E-bit count in a one second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues
to count if loss of multiframe sync occurs at the CAS level.
EBCR1: E-BIT COUNT REGISTER 1 (Address = 04 Hex)
EBCR2: E-BIT COUNT REGISTER 2 (Address = 05 Hex)
(MSB)
(LSB)
****
**
EB9
EB8
EBCR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EBCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
EB9
EBCR1.1
MSB of the 10-Bit E-Bit Error Count
EB0
EBCR2.0
LSB of the 10-Bit E-Bit Error Count
*The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.
FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12-bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is
disabled when RLOS is high. FAS errors are not counted when the framer is searching for FAS alignment
and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error
count in a one-second period is 4000, this counter cannot saturate.
FASCR1: FAS ERROR COUNT REGISTER 1 (Address = 02 Hex)
FASCR2: FAS ERROR COUNT REGISTER 2 (Address = 04 Hex)
(MSB)
(LSB)
FAS11
FAS10
FAS9
FAS8
FAS7
FAS6
(Note 2)
FASCR1
FAS5
FAS4
FAS3
FAS2
FAS1
FAS0
(Note 1)
FASCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
FAS11
FASCR1.7
MSB of the 12-Bit FAS Error Count
FAS0
FASCR2.2
LSB of the 12-Bit FAS Error Count
NOTES:
1) The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error
counter.
2) The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-bit counter.
相關PDF資料
PDF描述
DS21FT44 DATACOM, FRAMER, PBGA300
DS21Q352 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q41BT DATACOM, FRAMER, PQFP128
DS21Q42TN DATACOM, FRAMER, PQFP128
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