參數(shù)資料
型號： DS21FT44
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA300
封裝： 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁數(shù)： 56/117頁
文件大?。?/td> 691K
代理商： DS21FT44
DS21FT44/DS21FF44
43 of 117
to the status and information registers will be immediately followed by a read of the same register. The
read result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access by the
parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q44 with higher–order software languages.
The SSR register operates differently than the other three. It is a read only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt by the INT*
output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked
from the interrupt pin by the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and
HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 19.
The interrupts caused by four of the alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act
differently than the interrupts caused by other alarms and events in SR1 and SR2 (namely RSA1, RDMA,
RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). These four alarm interrupts
will force the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive
according to the set/clear criteria in Table 11-1). The INT* pin will be allowed to return high (if no other
interrupts are present) when the user reads the alarm bit that caused the interrupt to occur. If the alarm is
still present, the register bit will remain set.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
相關(guān)PDF資料
PDF描述
DS21Q352 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q354 DATACOM, PCM TRANSCEIVER, PBGA256
DS21Q41BT DATACOM, FRAMER, PQFP128
DS21Q42TN DATACOM, FRAMER, PQFP128
DS21Q42T DATACOM, FRAMER, PQFP128
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21FT44+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348B 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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