![](http://datasheet.mmic.net.cn/Maxim-Integrated-Products/DS2151QN_datasheet_97001/DS2151QN_7.png)
DS2151Q
7 of 60
PIN
NAME
TYPE
FUNCTION
20
BTS
I
Bus Type Select. Strap high to select Motorola bus timing; strap low to select
Intel bus timing. This pin controls the function of the
RD(DS), ALE(AS), and
WR(R/W) pins. If BTS = 1, then these pins assume the function listed in
parentheses.
21, 22
RTIP,
RRING
—
Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects
to a 1:1 transformer (see Section
13 for details).
23
RVDD
—
Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and TVDD
pins.
24
RVSS
—
Receive Signal Ground. 0V. Should be tied to local ground plane.
25, 26
XTAL1,
XTAL2
—
Crystal Connections. A pullable 6.176MHz crystal must be applied to these
pins. See Section
13 for crystal specifications.
27
INT1
O
Receive Alarm Interrupt 1. Flags host controller during alarm conditions
defined in Status Register 1. Active low, open drain output.
28
INT2
O
Receive Alarm Interrupt 2. Flags host controller during conditions defined
in Status Register 2. Active low, open drain output.
29
TTIP
—
Transmit Tip. Analog line driver output; connects to a step-up transformer
30
TVSS
—
Transmit Signal Ground. 0V. Should be tied to local ground plane.
31
TVDD
—
Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and
RVDD pins.
32
TRING
—
Transmit Ring. Analog line driver outputs; connects to a step-up transformer
33
TCHBLK
O
Transmit Channel Block. A user-programmable output that can be forced
high or low during any of the 24 T1 channels. Useful for blocking clocks to a
serial UART or LAPD controller in applications where not all T1 channels are
used such as Fractional T1, 384kbps service, 768kbps, or ISDN-PRI. Also
useful for locating individual channels in drop-and-insert applications. See
Section
14 for timing details.
34
TLCLK
O
Transmit Link Clock. 4kHz or 2kHz (ZBTSI) demand clock for the TLINK
input. See Section
14 for timing details.
35
TLINK
I
Transmit Link Data. If enabled via TCR1.2, this pin will be sampled during
the F-bit time on the falling edge of TCLK for data insertion into either the
FDL stream (ESF) or the Fs bit position (D4) or the Z-bit position (ZBTSI).
See Section
14 for timing details.
36
TSYNC
I/O
Transmit Sync. A pulse at this pin will establish either frame or multiframe
boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can be programmed
to output either a frame or multiframe pulse at this pin. If this pin is set to
output pulses at frame boundaries, it can also be set via TCR2.4 to output
double-wide pulses at signaling frames. See Section
14 for timing details.
37
DVDD
—
Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD pins.
38
TCLK
I
Transmit Clock. 1.544MHz primary clock.
39
TSER
I
Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge
of TCLK.
40
TCHCLK
O
Transmit Channel Clock. 192kHz clock that pulses high during the LSB of
each channel. Useful for parallel to serial conversion of channel data, locating
robbed-bit signaling bits, and for blocking clocks in DDS applications. See
Section
14 for timing details.