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參數(shù)資料
| 型號： | DS2149QN+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1 5V 28-PLCC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 500 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1/J1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
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DS2149
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9. SOFTWARE MODE
The DS2149 operates in software mode when the MODE1 pin is pulled high. In software mode, a
microprocessor controls the device and reads its status through the serial port, which provides access to
the internal registers. The host processor can completely configure the device as well as get diagnostics
and status reports through the serial port. In NRZ mode, bipolar violation insertions and logic error
insertions are controlled by the BPV and INSLER pins. Similarly, the recovered clock, data, and BPV
detection are available only at output pins. All other mode settings and diagnostic information are
available through the serial port. Figure 9-1 and Figure 9-2 show the serial port data structure. The
registers are accessible through a 16-bit word composed of an 8-bit command and address byte and a
subsequent 8-bit data byte. Software mode allows control of the output timing. The CLKE pin determines
when SDO is valid relative to SCLK and when receive data is valid relative to RCLK.
9.1 Interrupt Handling
In software mode, the DS2149 provides a latched interrupt output pin. When enabled, a change in any of
the status register bits generates an interrupt. When an interrupt occurs, the INT output pin is driven low.
The INT output pin structure is an open-drain only. Each device that shares the INT line requires an
external pullup resistor. The interrupt is cleared when the interrupt condition no longer exists, and a 1 is
written to the appropriate bit in the interrupt mask register. Leaving a 1 in any of the bits in the interrupt
mask register masks that interrupt. Clearing that bit re-enables the interrupt.
Table 9-A. CLKE Pin Selection
CLKE PIN
OUTPUT
OUTPUT UPDATED ON
RPOS
RNEG
RDATA
Falling RCLK
LOW
SDO
Rising SCLK
RPOS
RNEG
RDATA
Rising RCLK
HIGH
SDO
Falling SCLK
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