參數資料
| 型號： | DS2149QN+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1 5V 28-PLCC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 500 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1/J1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
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DS2149
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10.4Alarm Monitoring
10.4.1 Receive-Carrier Loss (RCL)
The receiver counts inbound 0s and declares RCL when the counter reaches 192. This applies to hardware
mode and software mode if the RCL2048 bit is cleared in CR4. In software mode, setting the RCL2048
bit changes the RCL counter to declare receive-carrier loss after 2048 consecutive 0s. Once set, the RCL
bit will remain set until the receiver detects a 12.5% density of 1s in a sliding window of 112 bits,
provided that there are no more than 98 consecutive 0s in that 112-bit window. When RCL is active,
RCLK is replaced by MCLK. RCL is indicated by an output high on the RCL pin and with a 1 in SR.0.
10.4.2 Alarm-Indication-Signal Detection (AIS)
AIS detection is only available in software mode. The receiver declares receipt of AIS when fewer than
six 0s are detected in 4632 bits (3ms). AIS is cleared when three or more 0s are received in 4632 bits. The
AIS bit in the status register (SR.2) indicates the presence of AIS. When the AIS status bit changes, the
AIS bit in the transition status register (TSR.2) is set. A change in the AIS status will generate an
interrupt if the AIS interrupt mask bit (IMR.2) bit is cleared.
10.4.3 Driver-Fail Monitor-Open (DFMO)
The DFMO bit is set in the status register when the transmitter outputs detect an open circuit. DFMO can
generate an interrupt if the DFMO interrupt mask bit (IMR.5) is cleared. This is not supported in
hardware mode.
10.4.4 Jitter Attenuator Limit Trip (JALT)
If the incoming jitter exceeds either 120 UIp-p (buffer depth is 128 bits) or 28 UIp-p (buffer depth is 32
bits), then the DS2149 will divide the internal nominal 24.704MHz (T1) clock by either 15 or 17 instead
of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also
sets the jitter attenuator limit trip (JALT) bit in information register 1 (IR1).
10.5Other Diagnostic Reports
10.5.1 Receive Line-Attenuation Indication
The device reports the approximate inbound signal strength in the status register (IR). The four most
significant bits indicate the signal strength in approximately 2.5dB increments.
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