參數(shù)資料
型號： DDC112U/1K
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： GREEN, PLASTIC, SOIC-28
文件頁數(shù)： 30/34頁
文件大?。?/td> 776K
代理商： DDC112U/1K
DDC112
5
SBAS085B
www.ti.com
CAP1A
AV
DD
NC
TEST
CONV
CLK
CAP2A
V
REF
AGND
NC
RANGE2 (MSB)
RANGE1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DDC112Y
CAP1B
AGND
IN1
IN2
AGND
CAP2B
32
31
30
29
28
27
26
25
DCLK
DXMIT
DIN
DV
DD
DGND
DOUT
DVALID
RANGE0
(LSB)
9
10
11
12
13
14
15
16
PIN CONFIGURATION
Top View
TQFP
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
1
CAP1A
External Capacitor for Integrator 1A
2
CAP1A
External Capacitor for Integrator 1A
3AVDD
Analog Supply, +5V Nominal
4
NC
No Connection
5
NC
No Connection
6
TEST
Test Control Input. When HIGH, a test charge is
applied to the A or B integrators on the next CONV
transition.
7
CONV
Controls which side of the integrator is connected to
input. In continuous mode; CONV HIGH side A is
integrating, CONV LOW side B is integrating CONV
must be synchronized with CLK (see text).
8
CLK
System Clock Input, 10MHz Nominal
9
DCLK
Serial Data Clock Input. This input operates the
serial I/O shift register.
10
DXMIT
Serial Data Transmit Enable Input. When LOW, this
input enables the internal serial shift register.
11
DIN
Serial Digital Input. Used to cascade multiple
DDC112s.
12
DVDD
Digital Supply, +5V Nominal
13
DGND
Digital Ground
14
DOUT
Serial Data Output, Hi-Z when DXMIT is HIGH
PIN
LABEL
DESCRIPTION
15
DVALID
Data Valid Output. A LOW value indicates valid data is
available in the serial I/O register.
16
RANGE0
Range Control Input 0 (least significant bit)
17
RANGE1
Range Control Input 1
18
RANGE2
Range Control Input 2. (most significant bit)
19
NC
No Connection
20
NC
No Connection
21
AGND
Analog Ground
22
VREF
External Reference Input, +4.096V Nominal
23
CAP2A
External Capacitor for Integrator 2A
24
CAP2A
External Capacitor for Integrator 2A
25
CAP2B
External Capacitor for Integrator 2B
26
CAP2B
External Capacitor for Integrator 2B
27
AGND
Analog Ground
28
IN2
Input 2: analog input for Integrators 2A and 2B. The
integrator that is active is set by the CONV input.
29
IN1
Input 1: analog input for Integrators 1A and 1B. The
integrator that is active is set by the CONV input.
30
AGND
Analog Ground
31
CAP1B
External Capacitor for Integrator 1B
32
CAP1B
External Capacitor for Integrator 1B
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