參數(shù)資料
型號: DAC5674IPHPG4
廠商: Texas Instruments
文件頁數(shù): 17/39頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 400MSPS 48-HTQFP
產(chǎn)品培訓模塊: Data Converter Basics
標準包裝: 250
系列: CommsDAC™
設置時間: 20ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 550mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應商設備封裝: 48-HTQFP(7x7)
包裝: 托盤
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 400M
配用: 296-30860-ND - EVAL MODULE FOR DAC5674
DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
24
Clock Input and Timing
Figure 27 shows the clock and data input timing diagram for internal and external clock modes, respectively.
Note that a negative value indicates a reversal of the edge positions as shown in the timing diagram. Figure 27
also shows the delay (td) of the 1×/2× data clock (PLLLOCK) from CLK in external clock mode (typical td = 4.1
ns). The latency from data to DAC is defined by Figure 28. The DAC5674 features a differential clock input.
In internal clock mode, the internal data clock is a divided down version of the PLL clock (/2 or /4), depending
on the level of interpolation (2
× or 4×). In external mode, the internal data clock is a divided down version of
the input CLK (/2 or /4), depending on the level of interpolation (2
× or 4×). Internal edge-triggered flip-flops latch
the input word on the rising edge of the positive data clock.
CLKC
PLLLOCK
D[13:0]
Valid Data
CLK
CLKC
D[13:0]
Valid Data
th
tsu
tlph
th
tsu
td_clk
Figure 27. Internal (Left) and External (Right) Clock Mode Timing
2x Interpolation
4x Interpolation
DAC
0
2000
3FFF
0
2000
0
Typical tsu = 0.5 ns, th = 0.1 ns
Typical tsu = 2.9 ns, th = 2.3 ns, td = 3.6 ns
D[13:0]
tlat_nx
Figure 28. Data to DAC Latency
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