參數(shù)資料
型號: DAC1208D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 65/98頁
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
65 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
Table 96.
Bit
6 to 0
INIT_SCR_S7T1_LN0 (address 12h) bit description
Symbol
INIT_VALUE_S7_S1_LN0[6:0]
Access
R/W
Value
00h
Description
initialization value for lane 0 descrambler bits s7 : s1
Table 97.
Bit
7 to 0
INIT_SCR_S15T8_LN1 register (address 13h) bit description
Symbol
INIT_VALUE_S15_S8_LN1[7:0]
Access
R/W
Value
00h
Description
initialization value for lane 1 descrambler bits
s15 : s8
Table 98.
Bit
6 to 0
INIT_SCR_S7T1_LN1 register (address 14h) bit description
Symbol
INIT_VALUE_S7_S1_LN1[6:0]
Access
R/W
Value
00h
Description
initialization value for lane 1 descrambler bits s7 : s1
Table 99.
Bit
7 to 0
INIT_SCR_S15T8_LN2 register (address 15h) bit description
Symbol
INIT_VALUE_S15_S8_LN2[7:0]
Access
R/W
Value
00h
Description
initialization value for lane 2 descrambler bits
s15 : s8
Table 100. INIT_SCR_S7T1_LN2 register (address 16h) bit description
Bit
Symbol
6 to 0
INIT_VALUE_S7_S1_LN2[6:0]
Access
R/W
Value
00h
Description
initialization value for lane 2 descrambler bits s7 : s1
Table 101. INIT_SCR_S15T8_LN3 register (address 17h) bit description
Bit
Symbol
7 to 0
INIT_VALUE_S15_S8_LN3[7:0]
Access
R/W
Value
00h
Description
initialization value for lane 3 descrambler bits
s15 : s8
Table 102. INIT_SCR_S7T1_LN3 register (address 18h) bit description
Bit
Symbol
6 to 0
INIT_VALUE_S7_S1_LN3[6:0]
Access
R/W
Value
00h
Description
initialization value for lane 3 descrambler bits s7 : s1
Table 103. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description
Bit
Symbol
7 to 4
INIT_ILA_BUFPTR_LN1[3:0]
3 to 0
INIT_ILA_BUFPTR_LN0[3:0]
Access
R/W
R/W
Value
8h
8h
Description
initialization value for lane 1 ILA buffer pointer
initialization value for lane 0 ILA buffer pointer
Table 104. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description
Bit
Symbol
7 to 4
INIT_ILA_BUFPTR_LN3[3:0]
3 to 0
INIT_ILA_BUFPTR_LN2[3:0]
Access
R/W
R/W
Value
8h
8h
Description
initialization value for lane 3 ILA buffer pointer
initialization value for lane 2 ILA buffer pointer
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