參數(shù)資料
型號: DAC1208D650HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述: 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 20/98頁
文件大?。?/td> 557K
代理商: DAC1208D650HN
DAC1208D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 December 2010
20 of 98
NXP Semiconductors
DAC1208D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A interface
10.2.5.4
All slave mode
The external reference is provided by the JESD204A transmitter. All DACs are configured
in slave mode.
The MDS signal is now driven from the transmitter. It is generated at the end of the
inter-lane alignment phase (see the JESD204A standard for details).
The transmitter must also compensate for the DAC latency. Although the DAC has an
internal samples delay line, it cannot handle large delays.
In this mode, PCB layout is also important. The following delay equation applies:
δ
t <
Δ
t
mds
< TDAC
δ
t, where
δ
t is the clock skew considered close to DAC pins.
Fig 11. All slave mode
001aal069
I
BUFFER
Q
DIG
COMP
ref_A
SYNC_0
JESD204A
TX
mds_out
mds_in
DAC
CLK
MGMT
I
BUFFER
Q
DIG
COMP
ref_A
SYNC_1
mds_out
mds_in
DAC
CLK
MGMT
I
BUFFER
SLAVE
DAC 0
SLAVE
DAC 1
SLAVE
DAC 2
Q
DIG
/A/
INSERTION
COMP
ref_A
SYNC_2
MDS
dT
mds_out
mds_in
DAC
CLK
MGMT
CLOCK
DISTRIBUTION
REF_CLOCK
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