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參數(shù)資料
| 型號： | CT1820 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | CT1820 Data Terminal Bit Processor for MIL-STD-1553 A & B |
| 中文描述： | CT1820數(shù)據(jù)終端位處理器的MIL - STD - 1553的阿 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 144K |
| 代理商： | CT1820 |
Aeroflex Circuit Technology
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
5
TRANSMIT CYCLE OPERATION
ENCODER SHIFT CLOCK (ESC) (see Figure 3)
operates at the data rate (1MHz). A low at
ENCODER ENABLE (ENC ENA) during a falling
edge of ESC
x
starts the Transmit cycle, which
lasts for twenty ESC clock periods. The SYNC
SELECT (SYNC SEL) input is valid at the next
low-to-high transition of ESC
y
. A high at SYNC
SEL will produce a data sync, or a low will produce
a command sync for that word.
Parallel data must be stable at the second rank
transmit register before SEND DATA goes high
z
.
Since ENC ENA is not synchronous with ESC, the
minimum time to
z
is 3μsec from ENC ENA leading
edge.
The first-rank transmit register may be operated
transparently (LATCH DATA always high), or may be
used to hold data ready for transmission,
independent of the activity on the 16-line subsystem
l/O bus. As long as LATCH DATA is held high, data
present on the subsystem l/O bus appears at the
output of the first rank transmit register. Stable data
may be latched and held at the first rank register
output by bringing LATCH DATA low. Data to be
transmitted may be latched any time before the
low-to high transition of SEND DATA (SEND DATA,
when appled to the LOAD DATA inputs, locks out
the data inputs to the second rank transmit
register.) For multiple word transmissions, the next
word may be inputted and latched any time after
z
,
but before the next low to-high transition of SEND
DATA.
SEND DATA remains high for 16 ESC periods,
during which the parallel transmit data is clocked to
the MANCHESTER ENCODER
z
to
{
. After the
sync and Manchester coded data are transmitted
through the DATA OUT and DATA OUT outputs, the
ENCODER adds on the parity bit for that word
|
.
If the transmitted word is to be the last word of the
transmission, ENC ENA must go high by
|
to
prevent initiation of another transmit cycle.
At any time, a low applied to OUTPUT INHIBIT will
force both DATA OUT and DATA OUT to a low state
without affecting any other operations.
The entire transmit cycle may be interrupted and
cleared by applying a minimum of 1μsec negative
pulse to the MASTER RESET (MRST) input.
For 8-BlT I/O subsystems, D0 is tied to D8, D1 to
D9, etc., through D7 tied to D15, and data is
inputted in 8-BlT bytes by using LATCH DATA 1 and
LATCH DATA 2 and / or LOAD DATA 1 and LOAD
DATA 2 independently.
For serial data applications, D15 input serves as the
serial transmit input. With LOAD DATA 1 held low
and LATCH DATA 1 held high, D15 input is applied
to the ENCODERís serial data input. Inputted data
must be at the ESC rate with the MSB starting at
the low-to-high transition of SEND DATA.
If a message length ever exceeds 768μsec, the
768μsec TIME OUT (FAIL SAFE) flag goes high,
and DATA OUT and DATA OUT are both forced to a
low state. This condition will remain until a valid
command word (containing the terminalís address)
is received or until MRST goes low.
SYNC
SYNC
15
14
13
2
1
0
P
SYNC
SYNC
15
14
13
2
1
0
P
SYNC
SYNC
15
14
13
2
1
0
P
SYNC
SYNC
15
14
13
2
1
0
P
4
5
0
1
2
3
4
5
16
17
18
19
0
1
2
3
4
5
16
17
18
19
3
2
1
VALID
DON’T CARE
DON’T CARE
DON’T CARE
DON’T CARE
VALID
SEE
SEE
DON’T CARE
ESC
SYNC SEL
ENC ENA
LATCH DATA
DATA SELECT
SEND DATA
& LOAD DATA
DATA OUT
DATA OUT
IF USED
DEPENDS ON "LATCH" TIMING
OPTIONAL NEXT-WORD LATCH
DEPENDS ON "LATCH" TIMING
OPTIONAL NEXT-WORD LATCH
Figure 3 – Transmit Cycle Timing
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