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參數(shù)資料
| 型號(hào)： | CT1820 |
| 廠商： | Aeroflex Inc. |
| 英文描述： | CT1820 Data Terminal Bit Processor for MIL-STD-1553 A & B |
| 中文描述： | CT1820數(shù)據(jù)終端位處理器的MIL - STD - 1553的阿 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 144K |
| 代理商： | CT1820 |
Aeroflex Circuit Technology
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
4
33
DEC RST
20
-0.4
20
-0.4
A LOW on this input (for 1μs minimum) resets the decoder
to a condition ready for a new word, resets the COMM /
DATA SYNC output LOW, and resets the VALID WORD
output HIGH.
34
GROUND
Logic and Power Return.
35
OUTPUT INH
20
-0.4
20
-0.4
A LOW on this input holds output pins 25 and 26 LOW.
36
SERIAL DATA OUT
-400
1.6
-400
4.0
4.0
The received serial data in NRZ format is available at this
pin during LOW TAKE DATA.
37
TAKE DATA
-360
2.4
-400
4.0
4.0
A LOW on this output indicates data shifting during the
receive cycle.
38
MRST
60
-1.2
20
-0.4
A LOW on this input (for 1μs minimum) interrupts and
clears the transmit cycle, resets the FAIL SAFE, and also
performs the same functions as DEC RST.
39
BROADCAST*
-300
1.6
-400
4.0
4.0
A HIGH on this output indicates reception of a valid
COMMAND (or STATUS) word containing all ONES in the
address field.
40
MODE CODE*
-600
2.4
-600
6.0
6.0
A LOW on this output indicates reception of a valid
COMMAND (or STATUS) word containing all ONES or all
ZEROS in the sub-address field.
41
D6
40
-0.4
-1000 2.4
20
-0.4 -1000
6.0
10.0
Part of 16 Bit TRI-STATE l/O
42
D7
43
DATA SELECT 2
20
-0.4
20
-0.4
A LOW on this input applies the contents of the SECOND
RANK REC’V REG to the D0-D7 I/O pins.
44
D5
40
-0.4
-1000 2.4
20
-0.4 -1000
6.0
10.0
Part of 16 Bit TRI-STATE l/O
45
D0
LSB of 16BIT TRI-STATE I/O
46
D1
Part of 16 Bit TRI-STATE l/O
47
D2
Part of 16 Bit TRI-STATE l/O
48
D3
Part of 16 Bit TRI-STATE l/O
49
LATCH DATA 2
20
-0.4
A HIGH on this input allows the l/O data on D0-D7 to
appear at the output of the FIRST RANK XMT REG. A
LOW on this input holds the register outputs in their last
state.
50
D4
40
-0.4
-1000 2.4
-1000
6.0
Part of 16 Bit TRl-STATE l/O
51
LOAD DATA 2
60
-1.2
A LOW on this input loads the D0-D7 data into the
SECOND RANK XMT REG. A HIGH on this input then
locks out the data inputs to permit serial shifting.
52
LATCH DATA 1
20
-0.4
A HIGH on this input allows the l/O data on D8-D15 to
appear at the output of the FIRST RANK XMT REG. A
LOW on this input holds the register outputs in their last
state.
53
LOAD DATA 1
60
-1.2
20
-0.4
A LOW on this input loads the D8-D15 data into the
SECOND RANK XMT REG. A HIGH on this input then
locks out the data inputs to permit serial shifting.
54
D13
40
-0.4
-1000 2.4
-1000
6.0
10.0
Part of 16 Bit TRl-STATE l/O.
OPTIONAL SERIAL INPUT.
55
D14
56
D15
Pin
No
Name
CT1555-3
CT1820
CT1820-2
Description
I
IH
(μA)
I
IL
(μA)
I
OH
(μA)
I
OL
(mA
I
IH
(μA)
I
IL
(μA)
I
OH
(μA)
I
OL
(mA
I
OL
(mA)
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