參數(shù)資料
型號: CS5524-ASZR
廠商: Cirrus Logic Inc
文件頁數(shù): 46/56頁
文件大?。?/td> 0K
描述: IC ADC 24BIT 4CH 24-SSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 14.8mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個差分,單極;4 個差分,雙極
配用: 598-1012-ND - EVAL BOARD FOR CS5524 ADC
CS5521/22/23/24/28
50
DS317F8
2.1 Clock Generator
XIN; XOUT - Crystal In; Crystal Out.
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device.
2.2 Control Pins and Serial Data I/O
CS - Chip Select.
When active low, the port will recognize SCLK. When high the SDO pin will output a high
impedance state. CS should be changed when SCLK = 0.
SDI - Serial Data Input.
SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.
SDO - Serial Data Output.
SDO is the serial data output. It will output a high impedance state if CS =1.
SCLK - Serial Clock Input.
A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins
respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin
will recognize clocks only when CS is low.
A0, A1 - Logic Outputs.
The logic states of A0-A1 mimic the states of the D22/D10-D23/D11 bits of the channel-setup
register. Logic Output 0 = AGND, and Logic Output 1 = VA+.
2.3 Measurement and Reference Inputs
AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- - Differential Analog Input.
Differential input pins into the CS5522 and CS5524 devices.
AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ - Single-Ended Analog Input.
Single-ended input pins into the CS5528.
VREF+, VREF- - Voltage Reference Input.
Fully differential inputs which establish the voltage reference for the on-chip modulator.
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