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參數(shù)資料
| 型號： | CS5524-ASZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 35/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 4CH 24-SSOP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 14.8mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 24-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個差分，單極；4 個差分，雙極 |
| 配用： | 598-1012-ND - EVAL BOARD FOR CS5524 ADC |
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CS5521/22/23/24/28
40
DS317F8
of the configuration register.
4) Once the CSRs are programmed, repeated conver-
sions on up to 16 Setups can be performed by is-
suing only one command byte.
5) The single conversion mode also requires only one
command, but whenever another or a different
single conversion is wanted, this command or a
modified version of it has to be issued again.
6) The NULL command is used to keep the serial port
in command mode, once it is in command mode.
1.5
Conversion Output Coding
The CS5521/22/23/24/28 devices output 16-bit
(CS5521/23) and 24-bit (CS5522/24/28) data con-
version words. To read a conversion word, the user
must read the conversion data FIFO. The conver-
sion data FIFO is up to 192 bits long and outputs
the conversions MSB first. The last byte of the con-
version data word (CS5521/23 only) contains data
monitoring flags. The channel indicator (CI) bits
keep track of which physical channel was convert-
ed, and the overrange flag (OF) and the oscillation
detect (OD) bits monitor conversions to determine
if a valid conversion was performed. Refer to the
Conversion Data FIFO Descriptions section for
more details.
The CS5521/22/23/24/28 output data conversions
in binary format when operating in unipolar mode
and in two's complement when operating in bipolar
mode. Refer to the Conversion Data FIFO De-
scriptions section for more details.
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the
voltage between
± full scale for any of the bipolar gain ranges. See text about error flags under overrange
conditions.
Unipolar Input
Voltage
Offset
Binary
Bipolar Input
Voltage
Two's
Complement
Unipolar Input
Voltage
Offset
Binary
Bipolar Input
Voltage
Two's
Complement
>(VFS-1.5 LSB)
FFFF
>(VFS-1.5 LSB)
7FFF
>(VFS-1.5 LSB) FFFFFF
>(VFS-1.5 LSB)
7FFFFF
VFS-1.5 LSB
FFFF
------
FFFE
VFS-1.5 LSB
7FFF
------
7FFE
VFS-1.5 LSB
FFFFFF
------
FFFFFE
VFS-1.5 LSB
7FFFFF
------
7FFFFE
VFS/2-0.5 LSB
8000
------
7FFF
-0.5 LSB
0000
------
FFFF
VFS/2-0.5 LSB
800000
------
7FFFFF
-0.5 LSB
000000
------
FFFFFF
+0.5 LSB
0001
------
0000
-VFS+0.5 LSB
8001
------
8000
+0.5 LSB
000001
------
000000
-VFS+0.5 LSB
800001
------
800000
<(+0.5 LSB)
0000
<(-VFS+0.5 LSB)
8000
<(+0.5 LSB)
000000
<(-VFS+0.5 LSB)
800000
Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28
CS5521/23 16-Bit Output Coding
CS5522/24/28 24-Bit Output Coding
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| CS5525-AS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Delta Sigma Multi-Range ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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