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參數(shù)資料
| 型號(hào)： | CH7008A-V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital PC to TV Encoder Features |
| 中文描述： | 數(shù)字電視編碼器電腦功能 |
| 文件頁數(shù)： | 24/49頁 |
| 文件大?。?/td> | 341K |
| 代理商： | CH7008A-V |
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CHRONTEL
CH7008A
24
201-0000-027 Rev 2.2, 9/30/99
Transfer Protocols
(continued)
AutoInc
Register Address Auto-Increment - to facilitate sequential R/W of registers.
“1”:
Auto-Increment enabled (auto-increment mode).
Write: After writing data into a register, the Address Register will automatically be
incremented by one.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will automatically be incremented by one.
However, for the first read after an RAB, the Address Register will not be changed.
“0”:
Auto-Increment disabled (alternating mode).
Write: After writing data into a register, the Address Register will remain unchanged until a
new RAB is written.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will remain unchanged.
AR[5:0]
Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7008. The R/W access, which
follows, is directed to the register specified by the content stored in the Address Register.
The following two sections describe the operation of the serial interface for the four combinations of R/W = 0,1 and
AutoInc = 0,1.
CH7008 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master-
transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave-
receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7008 always acknowledges for writes (see
Figure 19
). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
Figure 19: Acknowledge on the Bus
Figure 20
shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information,
following the Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If
AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.
SC from
Master
SD Data Output
By the CH7008
Start
Condition
2
SD Data Output
By Master-Transmitter
1
8
9
not acknowledge
acknowledge
clock pulse for
acknowledgment
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