參數(shù)資料
型號(hào)： CH7008A-V
廠商： Electronic Theatre Controls, Inc.
英文描述： Digital PC to TV Encoder Features
中文描述： 數(shù)字電視編碼器電腦功能
文件頁(yè)數(shù)： 12/49頁(yè)
文件大?。?/td> 341K
代理商： CH7008A-V
CHRONTEL
CH7008A
12
201-0000-027 Rev 2.2, 9/30/99
Display Modes
(continued)
additional filtering for enhancing the readability of text. These modes are fully programmable via I
2
C under the
flicker filter register.
Internal Voltage Reference
An on chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a
reference resistor at pin ISET, and register controlled divider, sets the output ranges of the DACs. The CH7008
bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal for PAL or NTSC-J,
which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor from ISET
to ground is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for
DAC output is 1/48
th
. Therefore, for each DAC, the current output per LSB step is determined by the following
equation:
I
LSB
= V(ISET)/ISET reference resistor * 1/GAIN
For DACG=0, this is: I
LSB
= 1.235/360 * 1/48 = 71.4
μ
A (nominal)
For DACG=1, this is: I
LSB
= 1.317/360 * 1/48 = 76.2
μ
A (nominal)
Power Management
The CH7008 supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off
and Composite Off to provide optimal power consumption for the application involved. Using the programmable
power down modes accessed over the I
2
C port, the CH7008 may be placed in either Normal state, or any of the four
power managed states, as listed below (see “Power Management Register” under the
Register Descriptions
section
for programming information). To support power management, a TV sensing function (see “Connection Detect
Register” under the
Register Descriptions
section) is provided, which identifies whether a TV is connected to either
S-Video or composite. This sensing function can then be used to enter into the appropriate operating state (e.g., if
TV is sensed only on composite, the S-Video Off mode could be set by software).
Table 8. Power Management
Luminance and Chrominance Filter Options
The CH7008 contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S-
Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown,
the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and
chrominance video bandwidth output is shown in
Table 9
.
Operating State
Normal (On):
Power Down:
Functional Description
In the normal operating state, all functions and pins are active.
In the power-down state, most pins and circuitry are disabled.The DS/BCO pin
will continue to provide either the VCO divided by K3, or 14.318 MHz out when
selected as an output, and the P-OUT pin will continue to output a clock
reference when in master clock mode.
Power is shut off to the unused DACs associated with S-Video outputs.
In Composite-off state, power is shut off to the unused DAC associated with
CVBS output.
In this power-down state, all but the I
2
C circuits are disabled. This places the
CH7008 in its lowest power consumption mode.
S-Video Off:
Composite Off:
Full Power Down:
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