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參數(shù)資料
| 型號： | CH1005C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital PC to TV Encoder with Macrovision |
| 中文描述： | 數(shù)碼電腦電視編碼器和通過Macrovision |
| 文件頁數(shù)： | 46/49頁 |
| 文件大?。?/td> | 338K |
| 代理商： | CH1005C |
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CHRONTEL
CH7005C
46
201-0000-025 Rev 2.1, 8/2/99
Register Descriptions
(continued)
CIV Control Register
Symbol: CIVC
Address: 21H
Bits: 5
The following controls are available through the CIV control register:
ACIV
When the automatic calculated increment value is 1, the number calculated and present at the CIV
registers will automatically be used as the increment value for subcarrier generation, removing the
need for the user to read the CIV value and write in a new FSCI value. Whenever this bit is set to
1, the subcarrier generation must be forced to free-run mode.
CIVH[1:0]
These bits control the hysteresis circuit which is used to calculate the CIV value.
CIV[25:24]
See descriptions in the next section.
Calculated Increment Value Register
Symbol: CIV
Address: 22H - 24H
Bits: 8
The CIV registers 22H through 24H contain a 26-bit value, which is the calculated increment value that should be
used as the upper 26 bits of FSCI. This value is determined by a comparison of the pixel clock and the 14MHz
clock. The bit locations and calculation of CIV are specified as the following:
Register
Contents
21H
CIV[25:24]
22H
CIV[23:16]
23H
CIV[15:8]
24H
CIV[7:0]
Version ID Register
Symbol: VID
Address: 25H
Bits: 8
This read-only register contains a 8-bit value indicating the identification number assigned to this version of the
CH7005. The default value shown is pre-programmed into this chip and is useful for checking for the correct
version of this chip, before proceeding with its programming.
Bit:
7
6
5
4
CIV25
3
CIV24
2
CIVH1
1
CIVH0
0
ACIV
Symbol:
Type:
R
R
R/W
R/W
R/W
Default:
0
0
0
0
1
Bit:
Symbol:
7
CIV#
6
CIV#
5
CIV#
4
CIV#
3
CIV#
2
CIV#
1
CIV#
0
CIV#
Type:
Default:
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit:
Symbol:
7
VID7
6
VID6
5
VID5
4
VID4
3
VID3
2
VID2
1
VID1
0
VID0
Type:
Default:
R
R
R
R
R
R
R
R
0
0
1
1
1
0
1
0
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