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參數(shù)資料
| 型號： | CH1005C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital PC to TV Encoder with Macrovision |
| 中文描述： | 數(shù)碼電腦電視編碼器和通過Macrovision |
| 文件頁數(shù)： | 29/49頁 |
| 文件大?。?/td> | 338K |
| 代理商： | CH1005C |
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201-0000-025 Rev 2.1, 8/2/99
29
CHRONTEL
CH7005C
Registers and Programming
The CH7005 is a fully programmable device, providing for full functional control through a set of registers accessed
from the I
2
C port. The CH7005 contains a total of 37 registers, which are listed in
Table 14
and described in detail
under
Register Descriptions
. Detailed descriptions of operating modes and their effects are contained in the previ-
ous section,
Functional Description.
An addition (+) sign in the Bits column below signifies that the parameter con-
tains more than 8 bits, and the remaining bits are located in another register.
Table 14. Register Map
Register
Symbol
DMR
FFR
VBW
IDF
CM
Address
00H
01H
03H
04H
06H
Bits
8
6
7
7
8
Functional Summary
Display Mode
Flicker Filter
Video Bandwidth
Input Data Format
Clock Mode
Display mode selection
Flicker filter mode selection
Luma and chroma filter bandwidth selection
Data format and bit-width selections
Sets the clock mode to be used
Start Active Video
SAV
07H
8+
Active video delay setting
Position Overflow
PO
08H
3
MSB bits of position values
Black level adjustment input latch clock edge select
Enables horizontal movement of displayed image on
TV
Black Level
BLR
HPR
09H
0AH
8
8+
Horizontal Position
Vertical Position
VPR
0BH
8+
Enables vertical movement of displayed image on
TV
Determines the horizontal and vertical sync polarity
Sync Polarity
Power Management
Connection Detect
Contrast Enhancement
PLL M and N extra bits
PLL-M Value
PLL-N Value
Buffered Clock
Subcarrier Frequency
Adjust
PLL and Memory Control
CIV Control
Calculated Fsc Increment
Value
Version ID
Test
SPR
0DH
4
PMR
CDR
CE
MNE
PLLM
PLLN
BCO
FSCI
0EH
10H
11H
13H
14H
15H
17H
18H -1FH
5
4
3
5
8+
8+
6
4 or 8
each
6
5
8 each
Enables power saving modes
Detection of TV presence
Contrast enhancement setting
Contains the MSB bits for the M and N PLL values
Sets the PLL M value - bits (7:0)
Sets the PLL N value - bits (7:0)
Determines the clock output at pin 41
Determines the subcarrier frequency
PLLC
CIVC
CIV
20H
21H
22H -
24H
25H
26H -
29H
3FH
Controls for the PLL and memory sections
Control of CIV value
Readable register containing the calculated
subcarrier increment value
Device version number
Reserved for test (details not included herein)
VID
TR
8
30
Address
AR
6
Current register being addressed
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