參數(shù)資料
型號(hào)： BU-62743
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？
文件頁(yè)數(shù)： 5/56頁(yè)
文件大小： 368K
代理商： BU-62743
5
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
INTRODUCTION
The BU-62743 RT, and BU-62843/62864 BC/RT/MT PCI
Enhanced Mini-ACE family of MIL-STD-1553 terminals comprise
a complete integrated interface between a PCI host processor
and a MIL-STD-1553 bus. All members of the PCI Enhanced
Mini-ACE family are packaged in the same 1.0 square inch flat-
pack package. The PCI Enhanced Mini-ACE hybrids provide
footprint and software compatibility with the Enhanced Mini-ACE,
Mini-ACE (Plus) terminals, as well as software compatibility with
the older ACE series.
The PCI Enhanced Mini-ACE provides complete multiprotocol
support of MIL-STD-1553A/B/McAir and STANAG 3838. All ver-
sions integrate dual transceiver; along with protocol, host inter-
face, memory management logic; and a minimum of 4K words of
RAM. In addition, the BU-62864 BC/RT/MT terminals include
64K words of internal RAM, with built-in parity checking.
The PCI Enhanced Mini-ACEs include a 5V, voltage source
transceiver for improved line driving capability, with options for
MIL-STD-1760 and McAir compatibility. To provide further flexi-
bility, the PCI Enhanced Mini-ACE may operate with a choice of
10, 12, 16, or 20 MHz clock inputs.
The PCI Enhanced Mini-ACEs are fully compliant targets, as
defined by the PCI Local Bus Specification Revision 2.2, using a
32 bit interface that operates at clock speeds of up to 33 MHz,
from a 3.3V bus. The interface supports PCI interrupts and con-
tains a FIFO that handles PCI burst write transfer cycles. The
FIFO is deep enough to accept an entire 1553 message.The PCI
interface is NOT 5V tolerant and cannot be used in a 5V PCI sig-
naling environment.The PCI interface is powered by 3.3V.
The 64K RAM, in the 64K version, is powered by 5V.
One of the new salient features of the PCI Enhanced Mini-ACE
is its Enhanced Bus Controller architecture.The Enhanced BC's
highly autonomous message sequence control engine provides
a means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
The PCI Enhanced Mini-ACE RT offers the choice of single and
circular buffering for individual subaddresses. New enhance-
ments to the RT architecture include a global circular buffering
option for multiple (or all) receive subaddresses, a 50% rollover
interrupt for circular buffers, an interrupt status queue for logging
up to 32 interrupt events, and an option to automatically initialize
to RT mode with the Busy bit set.The interrupt status queue and
50% rollover interrupt features are also included as improve-
ments to the PCI Enhanced Mini-ACE's Monitor architecture.
The PCI Enhanced Mini-ACE series terminals operate over the
full military temperature range of -55 to +125°C. Available
screened to MIL-PRF-38534C, the terminals are ideal for military
and industrial processor-to-1553 applications.
TRANSCEIVERS
The transceivers in the PCI Enhanced Mini-ACE series terminals
are fully monolithic, requiring only a +5V power input.The trans-
mitters are voltage sources, which provide improved line driving
capability over current sources. This serves to improve perform-
ance on long buses with many taps. The transmitters also offer
an option which satisfies the MIL-STD-1760 requirement for a
minimum of 20 volts peak-to-peak, transformer coupled output.
Besides eliminating the demand for an additional power supply,
the use of a +5V-only transceiver requires the use of a step-up,
rather than a step-down, isolation transformer.This provides the
advantage of higher terminal input impedance than is possible
for a 15 volt or 12 volt transmitter. As a result, there is a greater
margin for the input impedance test, mandated for the 1553 val-
idation test. This characteristic allows for longer cable lengths
between a system connector and the isolation transformers of an
embedded 1553 terminal.
To provide compatibility to McAir specs, the PCI Enhanced Mini-
ACE is available with an option for transmitters with increased
rise and fall times.
Additionally, for MIL-STD-1760 applications, the PCI Enhanced
Mini-ACE provides an option for a minimum stub voltage level of
20 volts peak-to-peak, transformer coupled.
The receiver sections of the PCI Enhanced Mini-ACE are fully
compliant with MIL-STD-1553B Notice 2 in terms of front-end
overvoltage protection, threshold, common mode rejection, and
word error rate.
PCI REGISTER AND MEMORY ADDRESSING
The PCI Interface contains a set of "Type 00h" PCI configuration
registers that are used to map the device into the host system.
There are two Base Address Registers that are used to imple-
ment ACE memory space (BAR0) and register space (BAR1).
The PCI configuration register space is mapped in accordance
with PCI revision 2.2 specifications.
The PCI Enhanced Mini-ACE acts as a target and responds to
the PCI commands listed in TABLE 2.
The PCI Enhanced Mini-ACE does NOT implement the Memory
Read Multiple, Memory Read Line or Memory Write and
Invalidate commands. However, in accordance with PCI rules,
the PACE will accept these requests and alias them to the basic
memory commands. For example, Memory Read Multiple and
相關(guān)PDF資料
PDF描述
BU-62843 MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
BU-62864 MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
BU-6486NEW MIL-STD-1553 Components |Mini-ACE? Mark3
BU-6586NEW MIL-STD-1553 Components |PCI Mini-ACE? Mark3
BU-69200 MIL-STD-1553 Components |ACE-Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BU-62843 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
BU-62864 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
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