參數(shù)資料
型號(hào): BU-62743
英文描述: MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述: 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇?
文件頁(yè)數(shù): 43/56頁(yè)
文件大小: 368K
代理商: BU-62743
43
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
FIGURE 15 shows the specific case of memory reads from the PCI-ACE interface registers at BAR1 800h-81Ch. Note that these reg-
isters are accessed quickly and without the Delayed Read Request (DRR) mechanism required by reads from the other memory loca-
tions (see next section).
1
2
3
4
5
6
7
PCI memory read from PCI-ACE interface register space (BAR1 800-81Ch)
ADRS
6h
Byte Enables
0ns
50ns
100ns
150ns
I
PCICLK
IO
AD
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
DATA
FIGURE 15. PCI READ OF PCI-ACE IF REGISTERS (BAR1 800-81 CH)
FIGURE 16 illustrates the process of reading an ACE memory (BAR0) or ACE register (BAR1 00-FCh) location.The actual read shown
is that of a single word read, due to the ~600 nS response time shown, see following text and timing formula tables. If the write FIFO
is empty and there isn't a previous Delayed Read Request (DRR) pending, a read from these locations enques a DRR, which is then
processed by the PACE. If either of these conditions is true, the PACE will respond with a Retry, but will not enque any new DRR.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
PCI memory read from ACE registers/memory with no DRR pending & FIFO empty
produces Retry & enques DRR. Master should attempt read as soon as possible
(preferably within 33 clocks). 3rd read produces disconnect with data, DRR complete
A
DAT
6h
6h
6h
0ns
250ns
500ns
750ns
I
PCICLK
IO
AD[31:0]
I
C/BE[3:0]#
I
FRAME#
I
IRDY#
O
TRDY#
O
STOP#
O
DEVSEL#
A
A
FIGURE 16. PCI READ OF ACE MEMORY/REGISTER
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