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參數(shù)資料
| 型號： | ATF1508RE-7AU100 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 45/54頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD EE 128MC 5NS 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 80 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 608 (CN2011-ZH PDF) |
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Introduction
1-2
Atmel ATF15xx Family: ISP Devices User Guide
1.1
Benefits
In-system programming allows you to program and reprogram devices after they are
soldered onto your circuit board. ISP eliminates the extra handling step required in the
manufacturing process to program the devices on an external programmer before plac-
ing them on your circuit board. Eliminating this step reduces the possibility of damaging
the delicate leads of high pin count surface mount devices or damaging the device
through electrostatic discharge (ESD). ISP also allows you to make design changes and
field upgrades without removing the Atmel ISP devices from the circuit board. In addi-
tion, ISP allows you to use your Automatic Test Equipment (ATE) to perform ISP
operations on your ISP devices and integrate these ISP operations with the normal pro-
duction test flow.
1.2
Atmel JTAG ISP
Interface
The Atmel JTAG ISP interface is a 4-pin, 3- or 5-volt interface compatible with the Joint
Test Action Group (JTAG) IEEE 1149.1a-1993 Standard. All Atmel ISP devices can be
programmed, verified and erased through this interface. The JTAG interface is a serial
interface consisting of the TCK, TMS, TDI and TDO signals, and a JTAG Test Access
Port (TAP) Controller. The TCK pin is the serial data clock. Programming data is clocked
by this pin. The TDI pin is the serial data input. It is used to shift programming data into
the Atmel device. The TDO pin is the serial data output. It is used to shift out data from
the Atmel device. The TMS pin is a mode select pin. It controls the state of the JTAG
TAP controller.
Atmel ISP devices are fully JTAG-compatible and support the required Boundary Scan
Test (BST) operations specified in the JTAG standard. Atmel ISP devices can be config-
ured to be a part of a JTAG BST chain with other JTAG devices for in-circuit testing of
your system board. With this feature, you can test Atmel CPLDs along with other
devices without resorting to bed-of-nails testing.
For more information about Atmel ISP, BST or the POF-to-JEDEC translator, please
contact Atmel PLD Applications at:
Hotline:
1-408-436-4333
E-mail:
pld@atmel.com
URL:
www.atmel.com
1.2.1
Single-device
Programming
The Atmel JTAG ISP interface can be configured to program a single Atmel ISP device.
The JTAG configuration for a single device is shown in Figure 1-1. When the Atmel ISP
device is configured in this way, a register appears between the TDI and TDO pins of
the device. The size of the register depends on the JTAG instruction width and the data
being shifted in for that instruction. The JTAG interface pins for the Atmel ISP device
must be connected to a 10-pin header on your circuit board. This header mates with the
ISP download cable and allows the Atmel-ISP software to transfer programming data
from your personal computer to the Atmel ISP device. The pinout for the JTAG pins for
different Atmel ISP devices is listed in Table 1-1.
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