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參數(shù)資料
| 型號： | AT90S8535-8PI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 47/127頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLSH 8MHZ A/D IT 40DIP |
| 標準包裝： | 18 |
| 系列： | AVR® 90S |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 8KB（4K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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26
AT90S/LS8535
1041H–11/01
sponding interrupt of External Interrupt Request 0 is executed from program memory
address $001. See also “External Interrupts.”
Bits 5.0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
General Interrupt Flag
Register – GIFR
Bit 7 – INTF1: External Interrupt Flag1
When an edge or logical change on the INT1 pin triggers an interrupt request, INTF1
becomes set (one). This flag is always cleared (0) when the pin is configured for low-
level interrupts, as the state of a low-level interrupt can be determined by reading the
PIN register.
If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the
interrupt address $002. For edge and logic change interrupts, this flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logi-
cal “1” to it.
Bit 6 – INTF0: External Interrupt Flag0
When an edge or logical change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). This flag is always cleared (0) when the pin is configured for low-
level interrupts, as the state of a low-level interrupt can be determined by reading the
PIN register.
If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the
interrupt address $001. For edge and logic change interrupts, this flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logi-
cal “1” to it.
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and always read as zero.
Timer/Counter Interrupt Mask
Register – TIMSK
Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $003) is executed if a compare match in Timer/Counter2 occurs (i.e., when the
OCF2 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set
in the Timer/Counter Interrupt Flag Register [TIFR]).
Bit
7
6
5
4
3
2
1
0
$3A ($5A)
INTF1
INTF0
––
–
GIFR
Read/Write
R/W
R
Initial Value
0
Bit
7
6
5
4
3
2
1
0
$39 ($59)
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
–
TOIE0
TIMSK
Read/Write
R/W
R
R/W
Initial Value
0
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