參數(shù)資料
型號： AT90S8535-8PI
廠商： Atmel
文件頁數(shù)： 39/127頁
文件大?。?/td> 0K
描述： IC MCU 8K FLSH 8MHZ A/D IT 40DIP
標準包裝： 18
系列： AVR® 90S
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： SPI，UART/USART
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 8KB（4K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
19
AT90S/LS8535
1041H–11/01
Status Register – SREG
The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable register is cleared (zero), none of the interrupts are enabled inde-
pendent of the individual interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s comple-
ment overflow flag V. See the Instruction Set description for detailed information.
Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the
Instruction Set description for detailed information.
Bit 2 – N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
See the Instruction Set description for detailed information.
Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logic operation. See the
Instruction Set description for detailed information.
Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-
tion Set description for detailed information.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
Bit
7
6
543210
$3F ($5F)
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
Initial Value
0
000000
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