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參數(shù)資料
| 型號： | AT90S8535-8PI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 46/127頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLSH 8MHZ A/D IT 40DIP |
| 標準包裝： | 18 |
| 系列： | AVR® 90S |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 連通性： | SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 8KB（4K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
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25
AT90S/LS8535
1041H–11/01
Interrupt Handling
The AT90S8535 has two 8-bit interrupt mask control registers: GIMSK (General Inter-
rupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding
interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until
the interrupt is enabled or the flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one) and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
General Interrupt Mask
Register – GIMSK
Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT1 is configured as an output. The corre-
sponding interrupt of External Interrupt Request 1 is executed from program memory
address $002. See also “External Interrupts.”
Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corre-
Table 6. Reset Source Identification
EXTRF
PORF
Reset Source
0
Watchdog Reset
0
1
Power-on Reset
1
0
External Reset
1
Power-on Reset
Bit
7
6
5
4
3
2
1
0
$3B ($5B)
INT1
INT0
––
–
GIMSK
Read/Write
R/W
R
Initial Value
0
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