參數(shù)資料
型號: ADV7391BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 60/108頁
文件大小: 0K
描述: IC ENCODER VIDEO W/DAC 32LFCSP
產(chǎn)品變化通告: ADV734x, ADV739x Feature Improvement
標(biāo)準包裝: 1
類型: 視頻編碼器
應(yīng)用: 機頂盒,視頻播放器,顯示器
電壓 - 電源,模擬: 2.6 V ~ 3.46 V
電壓 - 電源,數(shù)字: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤
配用: EVAL-ADV7391EBZ-ND - BOARD EVAL FOR ADV7391 ENCODER
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 55 of 108
ED/HD Sinc Compensation Filter Response
Subaddress 0x33, Bit 3
The ADV739x includes a filter designed to counter the effect of
sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in
ED/HD mode. This filter is enabled by default. It can be
disabled using Subaddress 0x33, Bit 3. The benefit of the filter is
Figure 67. ED/HD Sinc Compensation Filter Enabled
Figure 68. ED/HD Sinc Compensation Filter Disabled
ED/HD TEST PATTERN COLOR CONTROLS
Subaddress 0x36 to Subaddress 0x38
Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38
are used to program the output color of the internal ED/HD
test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it
be the lines of the crosshatch pattern or the uniform field test
pattern. They are not functional as color controls for external
pixel data input.
The values for the luma (Y) and color difference (Cr and Cb)
signals used to obtain white, black, and saturated primary and
complementary colors conform to the ITU-R BT.601-4
standard.
Table 44 shows sample color values that can be programmed
into the color registers when the output standard selection is set
to EIA770.2/EIA770.3 (Subaddress 0x30, Bits[1:0] = 00).
Table 44. Sample Color Values for EIA770.2/EIA770.3
ED/HD Output Standard Selection
Sample Color
Y Value
Cr Value
Cb Value
White
235
(0xEB)
128
(0x80)
128
(0x80)
Black
16
(0x10)
128
(0x80)
128
(0x80)
Red
81
(0x51)
240
(0xF0)
90
(0x5A)
Green
145
(0x91)
34
(0x22)
54
(0x36)
Blue
41
(0x29)
110
(0x6E)
240
(0xF0)
Yellow
210
(0xD2)
146
(0x92)
16
(0x10)
Cyan
170
(0xAA)
16
(0x10)
166
(0xA6)
Magenta
106
(0x6A)
222
(0xDE)
202
(0xCA)
COLOR SPACE CONVERSION MATRIX
Subaddress 0x03 to Subaddress 0x09
The internal color space conversion (CSC) matrix automatically
performs all color space conversions based on the input mode
programmed in the mode select register (Subaddress 0x01,
Bits[6:4]). Table 45 and Table 46 show the options available in
this matrix.
An SD color space conversion from RGB-in to YPrPb-out is
possible on the ADV7392/ADV7393. An ED/HD color space
conversion from RGB-in to YPrPb-out is not possible.
Table 45. SD Color Space Conversion Options
Input
Output1
YPrPb/RGB Out
(Subaddress 0x02,
Bit 5)
RGB In/YCrCb In
(Subaddress 0x87,
Bit 7)
YCrCb
YPrPb
1
0
YCrCb
RGB
0
YPrPb
1
RGB
0
1
CVBS/Y-C outputs are available for all CSC combinations.
2
Available on the ADV7392/ADV7393 (40-pin devices) only.
Table 46. ED/HD Color Space Conversion Options
Input
Output
YPrPb/RGB Out
(Subaddress 0x02, Bit 5)
YCrCb
YPrPb
1
YCrCb
RGB
0
SD Manual CSC Matrix Adjust Feature
The SD manual CSC matrix adjust feature (available for the
ADV7392 and ADV7393 only) provides custom coefficient
manipulation for RGB to YPbPr conversion (for YPbPr to RGB
conversion, this matrix adjustment is not available).
Normally, there is no need to modify the SD matrix coefficients
because the CSC matrix automatically performs the color space
conversion based on the output color space selected (see Table 46).
Note that Bit 7 in subaddress 0x87 must be set to enable RGB
input and, therefore, use the CSC manual adjustment.
FREQUENCY (MHz)
0.5
–0.5
30
5
0
G
AI
N
(
d
B)
10
15
20
25
0.4
0.1
–0.2
–0.3
–0.4
0.3
0.2
0
–0.1
06234-
068
FREQUENCY (MHz)
0.5
–0.5
30
5
0
G
AI
N
(
d
B)
10
15
20
25
0.4
0.1
–0.2
–0.3
–0.4
0.3
0.2
0
–0.1
06234-
069
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