參數(shù)資料
型號(hào): ADV7189BBSTZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 103/104頁(yè)
文件大?。?/td> 0K
描述: IC VIDEO DECODER SDTV 80-LQFP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 視頻解碼器
應(yīng)用: 機(jī)頂盒,視頻播放器,錄音機(jī)
電壓 - 電源,模擬: 3.15 V ~ 3.45 V
電壓 - 電源,數(shù)字: 1.65 V ~ 2 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤(pán)
ADV7189B
Rev. B | Page 98 of 104
DIGITAL INPUTS
The digital inputs on the ADV7189B are designed to work with
3.3 V signals, and are not tolerant of 5 V signals. Extra compo-
nents are needed if 5 V logic signals are required to be applied
to the decoder.
ANTIALIASING FILTERS
For inputs from some video sources that are not bandwidth
limited, signals outside the video band can alias back into the
video band during A/D conversion and appear as noise on the
output video. The ADV7189B oversamples the analog inputs
by a factor of 4. This 54 MHz sampling frequency reduces the
requirement for an input filter; for optimal performance it is
recommended that an antialiasing filter be employed. The
recommended low cost circuit for implementing this buffer and
filter circuit for all analog input signals is shown in
263H
Figure 45.
The buffer is a simple emitter-follower using a single npn
transistor. The antialiasing filter is implemented using passive
components. The passive filter is a third-order Butterworth
filter with a 3 dB point of 9 MHz. The frequency response of
the passive filter is shown in
264H
Figure 43. The flat pass band up to
6 MHz is essential. The attenuation of the signal at the output of
the filter due to the voltage divider of R24 and R63 is compen-
sated for in the ADV7189B part using the automatic gain
control. The ac-coupling capacitor at the input to the buffer
creates a high-pass filter with the biasing resistors for the
transistor. This filter has a cut-off of
{2 × π × (R39||R89) × C93}–1 = 0.62 Hz
It is essential the cutoff of this filter is less than 1 Hz to ensure
correct operation of the internal clamps within the part. These
clamps ensure that the video stays within the 5 V range of the
op amp used.
0
–20
–40
–60
–80
–100
–120
04983-0-040
100k
30M
10M
3M
1M
300k
300M
1G
100M
FREQUENCY (Hz)
Figure 43. Third-Order Butterworth Filter Response
CRYSTAL LOAD CAPACITOR VALUE SELECTION
265H
Figure 44 shows an example reference clock circuit for the
ADV7189B. Special care must be taken when using a crystal cir-
cuit to generate the reference clock for the ADV7189B. Small
variations in reference clock frequency can cause autodetection
issues and impair the ADV7189B performance.
Note:
Load capacitor values are dependent on crystal attributes.
The load capacitance given in a crystal data sheet specifies the
parallel resonance frequency within the tolerance at 25°C. It is
therefore important to design a circuit that matches the load
capacitance in order to achieve the frequency stipulated by the
manufacturer. For detailed crystal circuit design and optimiza-
tion, an application note on crystal design considerations is
available for further reference.
C1 = 47pF
C2 = 47pF
XTAL
28.63636MHz
XTAL
XTAL 1
04983-0-046
R = 1M
Ω
Figure 44. Crystal Circuit
Use the following guidelines to ensure correct operation:
Use the correct frequency crystal, which is
28.63636 MHz. Tolerance should be 50 ppm or better.
Use a parallel-resonant crystal.
Place a 1 MΩ shunt resistor across pins XTAL1 and
XTAL2 as is shown in Figure 45.
Know the CLOAD for the crystal part number selected.
The value of Capacitors C1 and C2 must match CLOAD
for the specific crystal part number in the user’s
system.
To find CLOAD use the following guideline:
C1 = C2 = C
C = 2(CLOAD CS) Cpg
Where Cpg is the pin to ground capacitance.
Approximately 4 pF to 10 pF.
CS is the PCB stray capacitance.
Approximately 2 pF to 3pF.
For example:
CLOAD = 30 pF
C = 2(30 3) 4
= 50 pF
Therefore two 47 pF capacitors can be chosen for
C1 and C2.
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