參數(shù)資料
型號: ADV7178
廠商: Analog Devices, Inc.
英文描述: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述: 綜合數(shù)字無線電咨詢委員會,601到PAL / NTSC制式視頻編碼器
文件頁數(shù): 7/38頁
文件大?。?/td> 280K
代理商: ADV7178
–7–
REV. 0
ADV7177/ADV7178
3.3 V TIMING SPECIFICATIONS
(V
AA
= +3.0 V–3.6 V
1
, V
REF
= 1.235 V, R
SET
= 300
V
. All specifications T
MIN
to T
MAX2
unless
otherwise noted.)
Parameter
MPU PORT
3, 4
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
ANALOG OUTPUTS
3, 5
Analog Output Delay
DAC Analog Output Skew
Conditions
Min
Typ
Max
Units
0
4.0
4.7
4.0
4.7
250
100
kHz
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
After This Period the First Clock Is Generated
Repeated for Start Condition
1
300
4.7
7
0
ns
ns
CLOCK CONTROL
AND PIXEL PORT
3, 4, 6
f
CLOCK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Control Setup Time, t
11
Control Hold Time, t
12
Digital Output Access Time, t
13
Digital Output Hold Time, t
14
Pipeline Delay, t
15
RESET CONTROL
3, 4
RESET
Low Time
27
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
8
8
3.5
4
4
3
24
4
37
6
ns
INTERNAL CLOCK CONTROL
Clock/2 Rise Time, t
16
Clock/2 Fall Time, t
17
OSD TIMING
4
OSD Setup Time, t
18
OSD Hold Time, t
19
10
10
ns
ns
10
2
ns
ns
NOTES
1
The max/min specifications are guaranteed over this range.
2
Temperature range T
MIN
to T
MAX
: 0
°
C to +70
°
C.
3
TTL input values are 0 to 3 volts, with input rise/fall times
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load
10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC
, FIELD/
VSYNC
,
BLANK
Clock Input:
CLOCK
Specifications subject to change without notice.
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