參數(shù)資料
型號: ADV7178
廠商: Analog Devices, Inc.
英文描述: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述: 綜合數(shù)字無線電咨詢委員會,601到PAL / NTSC制式視頻編碼器
文件頁數(shù): 17/38頁
文件大小: 280K
代理商: ADV7178
ADV7177/ADV7178
–17–
REV. 0
622
623
624
625
1
2
3
4
5
6
7
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
FIELD
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
FIELD
DISPLAY
320
Figure 19. Timing Mode 1 (PAL)
Mode 1: Master Option
HSYNC
,
BLANK
, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7177/ADV7178 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when
HSYNC
is low indicates a new frame, i.e., vertical retrace. The
BLANK
signal is optional. When the
BLANK
input is
disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge follow-
ing the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the
HSYNC
,
BLANK
and FIELD for an odd or even field transition relative to the pixel data.
FIELD
PIXEL
DATA
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Cb
Y
Cr
Y
HSYNC
BLANK
Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave
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