參數(shù)資料
型號(hào)： ADV7178
廠商： Analog Devices, Inc.
英文描述： Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述： 綜合數(shù)字無線電咨詢委員會(huì)，601到PAL / NTSC制式視頻編碼器
文件頁數(shù)： 27/38頁
文件大?。?/td> 280K
代理商： ADV7178
ADV7177/ADV7178
–27–
REV. 0
NTSC PEDESTAL REGISTERS 3–0 (PCE15–0, PCO15–0)
(Subaddress [SR4–SR0] = 11–0EH)
These 8-bit-wide registers are used to set up the NTSC pedestal
on a line-by-line basis in the vertical blanking interval for both
odd and even fields. Figure 40 show the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal OFF on the equivalent line when used in
NTSC.
FIELD 1/3
PCO6
PCO5
PCO3
PCO1
PCO4
PCO2
PCO0
PCO7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO14
PCO13
PCO11
PCO9
PCO12
PCO10
PCO8
PCO15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
FIELD 2/4
PCE6
PCE5
PCE3
PCE1
PCE4
PCE2
PCE0
PCE7
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE14
PCE13
PCE11
PCE9
PCE12
PCE10
PCE8
PCE15
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
Figure 40. Pedestal Control Registers
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 12H)
Mode Register 3 is an 8-bit-wide register.
Figure 41 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30)
This bit is read only and indicates the revision of the device.
VBI Pass-Through Control (MR31)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked.
Clock Output Select (MR33–MR32)
These bits control the synchronous clock output signal. The
clock can be 27 MHz, 13.5 MHz or disabled, depending on the
values of these bits.
OSD Enable (MR35)
A logic one in MR35 will enable the OSD function on the
ADV7177.
Reserved (MR36)
These bits are reserved.
Input Default Color (MR36)
This bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical
“1” forces the output color to black for 00000000 input video
data.
OSD REGISTER 0–11
(Address [SR4–SR0] = 12H–1DH)
There are 12 OSD registers as shown in Figure 42. There are
four bits for each Y, Cb and Cr value, there are four zero added
to give the complete byte for each value loaded internally.
(Y0 = [Y0
3
, Y0
2
, Y0
1
, Y0
0
, 0, 0, 0, 0], Cb = [Cb
3
, Cb
2
, Cb
1
,
Cb
0
, 0, 0, 0, 0,], Cr = [Cr
3
, Cr
2
, Cr
1
, Cr
0
, 0, 0, 0, 0].)
MR31
MR30
MR37
MR32
MR34
MR33
MR35
MR36
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR34
INPUT DEFAULT COLOR
0
1
INPUT COLOR
BLACK
MR36
VBI PASSTHROUGH
0 DISABLE
1 ENABLE
MR31
CLOCK CONTROL
0
0
1
1
0
1
0
1
CLOCK OUTPUT OFF
13.5MHz OUTPUT
27MHz OUTPUT
CLOCK OUTPUT OFF
MR33-32
MR30
REV CODE
(READ ONLY)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR37
OSD ENABLE
0 DISABLE
1 ENABLE
MR35
Figure 41. Mode Register 3
Y0
Cr0
Cb0
Y1
Cr1
Cb1
Cr7
Cb7
OSD
REG 0
OSD
REG 1
OSD
REG 2
OSD
REG 11
Figure 42. OSD Registers
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PDF描述
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