參數(shù)資料
型號(hào): ADV7178
廠商: Analog Devices, Inc.
英文描述: Integrated Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述: 綜合數(shù)字無線電咨詢委員會(huì),601到PAL / NTSC制式視頻編碼器
文件頁數(shù): 18/38頁
文件大?。?/td> 280K
代理商: ADV7178
ADV7177/ADV7178
–18–
REV. 0
Mode 2: Slave Option
HSYNC
,
VSYNC
,
BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7177/ADV7178 accepts horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC
and
VSYNC
inputs indicates the start of an odd field. A
VSYNC
low transition when
HSYNC
is high indicates the start of an even field.
The
BLANK
signal is optional. When the
BLANK
input is disabled, the ADV7177/ADV7178 automatically blanks all normally
blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
DISPLAY
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
HSYNC
BLANK
VSYNC
Figure 21. Timing Mode 2 (NTSC)
622
623
624
625
1
2
3
4
5
6
7
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
HSYNC
BLANK
DISPLAY
320
VSYNC
Figure 22. Timing Mode 2 (PAL)
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