參數(shù)資料
型號(hào)： ADV611JSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/46頁(yè)
文件大?。?/td> 0K
描述： IC CCTV DGTL VIDEO CODEC 120LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 8 b
三角積分調(diào)變： 無(wú)
電壓 - 電源，數(shù)字： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 120-LQFP
供應(yīng)商設(shè)備封裝： 120-LQFP（14x14）
包裝： 托盤(pán)
ADV611/ADV612
–41–
REV. 0
Table XXVII. Host (Indirect Address, Indirect Data and Interrupt Mask/Status) Write Timing Parameters
Parameter
Description
Min
Max
Unit
tWR_D_WRC
WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK)
N/A
1
N/A
ns
tWR_D_PWA
WR Signal, Direct Register, Pulsewidth Asserted (at 27 MHz VCLK)
N/A
1
N/A
ns
tWR_D_PWD
WR Signal, Direct Register, Pulsewidth Deasserted (at 27 MHz VCLK)
5
N/A
ns
tADR_D_WRS
ADR Bus, Direct Register, Write Setup
2
N/A
ns
tADR_D_WRH
ADR Bus, Direct Register, Write Hold
2
N/A
ns
tDATA_D_WRS
DATA Bus, Direct Register, Write Setup
–10
N/A
ns
tDATA_D_WRH
DATA Bus, Direct Register, Write Hold
0
N/A
ns
tWR_D_RDT
WR Signal, Direct Register, Read Turnaround (After a Write) (at 27 MHz VCLK)
35.6
2
N/A
ns
tACK_D_WRD
ACK Signal, Direct Register, Write Delay (at 27 MHz VCLK)
8.6
182.1
3, 4
ns
tACK_D_WROH
ACK Signal, Direct Register, Write Output Hold
11
N/A
ns
NOTES
1
WR input must be asserted (low) until ACK is asserted (low).
2Minimum t
WR_D_RDT varies with VCLK according to the formula: tWR_D_RDT (MIN) = 0.8 (VCLK Period) +7.4.
3Maximum t
WR_D_WRD varies with VCLK according to the formula: t ACK_D_WRD (MAX) = 4.3 (VCLK Period) +14.8.
4During STATS_R deasserted (low) conditions, t
ACK_D_WRD may be as long as 52 VCLK periods.
VALID
(I) ADR,
BE, CS
(I)
WR
(I) DATA
(O)
ACK
(I)
RD
t
ADR D WRS
t
DATA D WRS
t
WR D WRC
t
WR D PWA
t
WR D PWD
t
ADR D WRH
t
DATA D WRH
t
ACK D WRD
t
WR D RDT
t
ACK D WROH
Figure 33. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Timing
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