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參數(shù)資料
| 型號： | ADV611JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCTV DGTL VIDEO CODEC 120LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻編解碼器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP |
| 供應商設備封裝： | 120-LQFP（14x14） |
| 包裝： | 托盤 |
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ADV611/ADV612
–19–
REV. 0
DRAM Interface Pins
Name
Pins
I/O
Description
DDAT[15:0]
16
I/O
DRAM Data Bus. The ADV611/ADV612 uses these pins for 16-bit data read/
write operations to the external 256K
× 16-bit DRAM. (The operation of the
DRAM interface is fully automatic and controlled by internal functionality
of the ADV611/ADV612.) These pins are compatible with 30 pF loads.
DADR[8:0]
9
O
DRAM Address Bus. The ADV611/ADV612 uses these pins to form the multi-
plexed row/column address lines to the external DRAM. (The operation of the
DRAM interface is fully automatic and controlled by internal functionality
of the ADV611/ADV612.) These pins are compatible with 30 pF loads.
RAS
1
O
DRAM Row Address Strobe. This pin is compatible with 30 pF loads.
CAS
1
O
DRAM Column Address Strobe. This pin is compatible with 30 pF loads.
WE
1
O
DRAM Write Enable. This pin is compatible with 30 pF loads.
Note that the ADV611/ADV612 does not have a DRAM OE pin. Tie the
DRAM’s OE pin to ground.
Host Interface Pins
Name
Pins
I/O
Description
DATA[31:0]
32
I/O
Host Data Bus. These pins make up a 32-bit wide host data bus. The host
controls this asynchronous bus with the WR, RD, BE and CS pins to commu-
nicate with the ADV611/ADV612. These pins are compatible with 30 pF loads.
ADR[1:0]
2
I
Host DWord Address Bus. These two address pins let you address the
ADV611/ADV612’s four directly addressable host interface registers. For an
illustration of how this addressing works, see the Control and Write Register
Map figure and Status and Read Register Map figure. The ADR bits permit
register addressing as follows:
ADR1
ADR0
DWord
Address Byte Address
0
0x00
0
1
0x04
1
0
2
0x08
1
3
0x0C
BE0–BE1
2
I
Host Word Enable pins. These two input pins select the words that the ADV611/
BE2–BE3
ADV612’s direct and indirect registers access through the Host Interface;
BE0–BE1 access the least significant word, and BE2–BE3 access the most
significant word. For a 32-bit interface only, tie these pins to ground, making
all words available.
Some important notes for 16-bit interfaces are as follows:
When using these byte enable pins, the byte order is always the lowest byte
to the higher bytes.
The ADV611/ADV612 advances to the next 32-bit compressed data FIFO
location after the BE2–BE3 pin is asserted then de-asserted (when accessing the
Compressed Data register); so the FIFO location only advances when and if
the host reads or writes the MSW of a FIFO location.
The ADV611/ADV612 advances to the next 16-bit indirect register after the
BE0–BE1 pin is asserted then de-asserted; so the register selection only advances
when and if the host reads or writes the MSW of a 16-bit indirect register.
CS
1
I
Host Chip Select. This pin operates as follows:
LO Qualifies Host Interface control signals
HI Three-states DATA[31:0] pins
WR
1
I
Host Write. Host register writes occur on the rising edge of this signal.
RD
1
I
Host Read. Host register reads occur on the low true level of this signal.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV611JSTZ | 制造商:Analog Devices 功能描述:IC VIDEO CODEC |
| ADV612 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Closed Circuit TV Digital Video Codec |
| ADV612BST | 制造商:Analog Devices 功能描述:Video Compression 120-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:INDUSTRIAL GRADE CCTV DIGITAL VID CODEC - Tape and Reel |
| ADV65056509 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV65909302 | 制造商:LG Corporation 功能描述:Frame Assembly |
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