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參數(shù)資料
| 型號： | ADUC843BSZ62-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/88頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 52-MQFP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 47 of 88
Using the SPI Interface
Depending on the configuration of the bits in the SPICON SFR
shown in Table 18, the ADuC841/ADuC842/ADuC843 SPI
interface transmits or receives data in a number of possible
modes. Figure 54 shows all possible SPI configurations for the
parts, and the timing relationships and synchronization
between the signals involved. Also shown in this figure is the
SPI interrupt bit (ISPI) and how it is triggered at the end of each
byte-wide communication.
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
?
MSB BIT 6 BIT 5
?
BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
03260-
0-
053
Figure 54. SPI Timing, All Modes
SPI Interface—Master Mode
In master mode, the SCLOCK pin is always an output and
generates a burst of eight clocks whenever user code writes to
the SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. Also note that the SS pin is not
used in master mode. If the parts need to assert the SS pin on an
external slave device, a port digital output pin should be used.
In master mode, a byte transmission or reception is initiated by
a write to SPIDAT. Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.
With each SCLOCK period, a data bit is also sampled via MISO.
After eight clocks, the transmitted byte will be completely
transmitted, and the input byte will be waiting in the input shift
register. The ISPI flag will be set automatically, and an interrupt
will occur if enabled. The value in the shift register will be
latched into SPIDAT.
SPI Interface—Slave Mode
In slave mode, SCLOCK is an input. The SS pin must also be
driven low externally during the byte communication. Trans-
mission is also initiated by a write to SPIDAT. In slave mode, a
data bit is transmitted via MISO, and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte will be completely transmitted, and the
input byte will be waiting in the input shift register. The ISPI
flag will be set automatically, and an interrupt will occur if
enabled. The value in the shift register will be latched into
SPIDAT only when the transmission/reception of a byte has
been completed. The end of transmission occurs after the
eighth clock has been received if CPHA = 1, or when SS returns
high if CPHA = 0.
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