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| 型號(hào)： | ADUC843BSZ62-5 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/88頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 52-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 738 (CN2011-ZH PDF) |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 21 of 88
ACCUMULATOR SFR (ACC)
ACC is the accumulator register and is used for math opera-
tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the accumulator as A.
B SFR (B)
The B register is used with the ACC for multiplication and
division operations. For other instructions, it can be treated as a
general-purpose scratchpad register.
Stack Pointer (SP and SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the top of the stack. The SP register
is incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset, which
causes the stack to begin at location 08H.
As mentioned earlier, the parts offer an extended 11-bit stack
pointer. The 3 extra bits used to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7H.
Data Pointer (DPTR)
The data pointer is made up of three 8-bit registers named DPP
(page byte), DPH (high byte), and DPL (low byte). These are
used to provide memory addresses for internal and external
code access and for external data access. They may be manipu-
lated as a 16-bit register (DPTR = DPH, DPL), although INC
DPTR instructions automatically carry over to DPP, or as three
independent 8-bit registers (DPP, DPH, DPL). The parts support
dual data pointers. Refer to the Dual Data Pointer section.
Program Status Word (PSW)
The PSW SFR contains several bits reflecting the current status
of the CPU, as detailed in Table 5.
SFR Address
D0H
Power-On Default
00H
Bit Addressable
Yes
Table 5. PSW SFR Bit Designations
Bit
Name
Description
7
CY
Carry Flag.
6
AC
Auxiliary Carry Flag.
5
F0
General-Purpose Flag.
4
RS1
Register Bank Select Bits.
3
RS0
RS1
0
1
RS0
0
1
0
1
Selected Bank
0
1
2
3
2
OV
Overflow Flag.
1
F1
General-Purpose Flag.
0
P
Parity Bit.
Power Control SFR (PCON)
The PCON SFR contains bits for power-saving options and
general-purpose status flags, as shown in Table 6.
SFR Address
87H
Power-On Default
00H
Bit Addressable
No
Table 6. PCON SFR Bit Designations
Bit No.
Name
Description
7
SMOD
Double UART Baud Rate.
6
SERIPD
I2C/SPI Power-Down Interrupt Enable.
5
INT0PD
INT0 Power-Down Interrupt Enable.
4
ALEOFF
Disable ALE Output.
3
GF1
General-Purpose Flag Bit.
2
GF0
General-Purpose Flag Bit.
1
PD
Power-Down Mode Enable.
0
IDL
Idle Mode Enable.
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