LVDD S 2.5 V Output of t" />
參數資料
型號： ADUC7129BSTZ126
廠商： Analog Devices Inc
文件頁數： 9/92頁
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 80-LQFP
產品培訓模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數： 38
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數據轉換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 托盤
ADuC7128/ADuC7129
Rev. 0 | Page 17 of 92
Pin
No.
Mnemonic
Type1
Description
21
LVDD
S
2.5 V Output of the On-Chip Voltage Regulator. Must be connected to a 0.47 μF capacitor
to DGND.
22
DGND
S
Ground for Core Logic.
23
P3.0/PWM1
I/O
General-Purpose Input and Output Port 3.0/PWM1 Output.
24
P3.1/PWM2
I/O
General-Purpose Input and Output Port 3.1/PWM2 Output.
25
P3.2/PWM3
I/O
General-Purpose Input and Output Port 3.2/PWM3 Output.
26
P3.3/PWM4
I/O
General-Purpose Input and Output Port 3.3/PWM4 Output.
27
P0.3/ADCBUSY/TRST
I/O
General-Purpose Input and Output Port 3.3/ADCBUSY Signal/JTAG Test Port Input, Test Reset.
Debug and download access.
28
RST
I
Reset Input (Active Low).
29
P3.4/PWM5
I/O
General-Purpose Input and Output Port 3.4/PWM5 Output.
30
P3.5/PWM6
I/O
General-Purpose Input and Output Port 3.5/PWM6 Output.
31
P0.4/IRQ0/CONVST
I/O
General-Purpose Input and Output Port 0.5/External Interrupt Request 0, Active High/Start
Conversion Input Signal for ADC.
32
P0.5/IRQ1/ADCBUSY
I/O
General-Purpose Input and Output Port 0.6/External Interrupt Request 1, Active High/ADCBUSY
Signal.
33
P2.0/SPM9
I/O
General-Purpose Input and Output Port 2.0/Serial Port Mux Pin 9.
34
P0.7/SPM8/ECLK/XCLK
I/O
General-Purpose Input and Output Port 0.7/Serial Port Mux Pin 8/Output for the External
Clock Signal/Input to the Internal Clock Generator Circuits.
35
XCLKO
O
Output from the Crystal Oscillator Inverter.
36
XCLKI
I
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
37
PVDD
S
2.5 V PLL Supply. Must be connected to a 0.1 μF capacitor to DGND. Should be connected to
2.5 V LDO output.
38
DGND
S
Ground for PLL.
39
P1.7/SPM7
I/O
General-Purpose Input and Output Port 1.7/Serial Port Mux Pin 7.
40
P1.6/SPM6
I/O
General-Purpose Input and Output Port 1.6/Serial Port Mux Pin 6.
43
P4.0/S1
I/O
General-Purpose Input and Output Port 4.0/Quadrature Input 1.
44
P4.1/S2
I/O
General-Purpose Input and Output Port 4.1/Quadrature Input 2.
45
P1.5/SPM5
I/O
General-Purpose Input and Output Port 1.5/Serial Port Mux Pin 5.
46
P1.4/SPM4
I/O
General-Purpose Input and Output Port 1.4/Serial Port Mux Pin 4.
47
P1.3/SPM3
I/O
General-Purpose Input and Output Port 1.3/Serial Port Mux Pin 3.
48
P1.2/SPM2
I/O
General-Purpose Input and Output Port 1.2/Serial Port Mux Pin 2.
49
P1.1/SPM1
I/O
General-Purpose Input and Output Port 1.1/Serial Port Mux Pin 1.
50
P1.0/SPM0
I/O
General-Purpose Input and Output Port 1.0/Serial Port Mux Pin 0.
51
P4.2
I/O
General-Purpose Input and Output Port 4.2.
52
P4.3/ PWMTRIP
I/O
General-Purpose Input and Output Port 4.3/PWM Safety Cutoff.
53
P4.4
I/O
General-Purpose Input and Output Port 4.4.
54
P4.5
I/O
General-Purpose Input and Output Port 4.5.
55
VREF
I/O
2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the
internal reference.
56
DACGND
S
Ground for the DAC. Typically connected to AGND.
59
DACVDD
S
Power Supply for the DAC. This must be supplied with 2.5 V. This can be connected to the LDO
output.
60
ADC0
I
Single-Ended or Differential Analog Input 0.
61
ADC1
I
Single-Ended or Differential Analog Input 1.
62
ADC2/CMP0
I
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
63
ADC3/CMP1
I
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
64
ADC4
I
Single-Ended or Differential Analog Input 4.
1 I = input, O = output, S = supply.
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