參數(shù)資料
型號(hào)： ADUC7129BSTZ126
廠商： Analog Devices Inc
文件頁數(shù)： 30/92頁
文件大小： 0K
描述： IC DAS MCU ARM7 ADC/DDS 80-LQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 38
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 托盤
ADuC7128/ADuC7129
Rev. 0 | Page 36 of 92
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture is described for the three different modes of
operation: differential mode, pseudo differential mode, and
single-ended mode.
Differential Mode
The ADuC7128/ADuC7129 contain a successive approximation
ADC based on two capacitive DACs. Figure 37 and Figure 38
show simplified schematics of the ADC in acquisition and
conversion phase, respectively. The ADC comprises control logic,
a SAR, and two capacitive DACs. In Figure 37 (the acquisition
phase), SW3 is closed and SW1 and SW2 are in Position A. The
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN13
MUX
CHANNEL+
CHANNEL–
06020-
033
Figure 37. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 38), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic generates
the ADC output code. The output impedances of the sources
driving the VIN+ pin and the VIN pin must be matched; otherwise,
the two inputs have different settling times, resulting in errors.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN13
MUX
CHANNEL+
CHANNEL–
0602
0-
03
4
Figure 38. ADC Conversion Phase
Pseudo Differential Mode
In pseudo differential mode, Channel is linked to the VIN pin
of the ADuC7128/ADuC7129, and SW2 switches between A
(Channel) and B (VREF). The VIN pin must be connected to
ground or a low voltage. The input signal on VIN+ can then vary
from VIN to VREF + VIN. Note that VIN must be chosen so that
VREF + VIN does not exceed AVDD.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
AIN0
AIN13
VIN–
MUX
CHANNEL+
CHANNEL–
0602
0-
03
5
Figure 39. ADC in Pseudo Differential Mode
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The VIN pin can be floating. The input signal range on
VIN+ is 0 V to VREF.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
CS
AIN0
AIN13
MUX
CHANNEL+
CHANNEL–
0602
0-
03
6
Figure 40. ADC in Single-Ended Mode
Analog Input Structure
Figure 41 shows the equivalent circuit of the analog input
structure of the ADC. The four diodes provide ESD protection
for the analog inputs. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
300 mV. Voltage in excess of 300 mV would cause these diodes to
become forward biased and start conducting into the substrate.
These diodes can conduct up to 10 mA without causing
irreversible damage to the part.
The C1 capacitors in Figure 41 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 100 Ω. The C2 capacitors
are the ADC sampling capacitors and have a capacitance of 16 pF
typical.
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