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參數(shù)資料
| 型號： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 77/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標準包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 79 of 92
TIMER3—WATCHDOG TIMER
TIMER3IRQ
16-BIT LOAD
16-BIT
UP/DOWN
COUNTER
TIMER3 VALUE
PRESCALER
1, 16, OR 256
WATCHDOG
RESET
LOW POWER
32.768kHz
06
02
0-
05
3
Figure 58. Timer3 Block Diagram
Timer3 has two modes of operation: normal mode and
watchdog mode. The watchdog timer is used to recover from an
illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a reset of the processor.
Timer3 reloads the value from T3LD either when Timer3
overflows or immediately after T3ICLR is written.
Normal Mode
The Timer3 in normal mode is identical to Timer0 in 16-bit
mode of operation, except for the clock source. The clock source
is the 32.768 kHz oscillator and can be scaled by a factor of 1,
16, or 256. Timer3 also features a capture facility that allows
capture of the current timer value if the Timer2 interrupt is
enabled via IRQEN[5].
Watchdog Mode
Watchdog mode is entered by setting T3CON[5]. Timer3 decre-
ments from the timeout value present in the T3LD register to 0.
The maximum timeout is 512 seconds, using the maximum
prescalar/256 and full scale in T3LD.
User software should only configure a minimum timeout
period of 30 ms. This is to avoid any conflict with Flash/EE
memory page erase cycles, which require 20 ms to complete
a single page erase cycle and kernel execution.
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
can be written to T3ICLR before T3VAL reaches 0. This reloads
the counter with T3LD and begins a new timeout period.
Once watchdog mode is entered, T3LD and T3CON are write
protected. These two registers cannot be modified until a
power-on reset event resets the watchdog timer. After any other
reset event, the watchdog timer continues to count. The
watchdog timer should be configured in the initial lines of user
code to avoid an infinite loop of watchdog resets.
Timer3 is automatically halted during JTAG debug access and
only recommences counting once JTAG has relinquished control
of the ARM7 core. By default, Timer3 continues to count during
power-down. This can be disabled by setting Bit 0 in T3CON. It is
recommended that the default value is used, that is, the watchdog
timer continues to count during power-down.
Timer3 Interface
The Timer3 interface consists of four MMRs, as shown in Table 114.
Table 114. Timer3 Interface MMRs
Name
Description
T3CON
The configuration MMR (see Table 115).
T3LD
A 16-bit register (Bit 0 to Bit15). Holds 16-bit
unsigned integers.
T3VAL
A 16-bit register (Bit 0 to Bit 15). Holds 16-bit
unsigned integers. This register is read only.
T3ICLR
An 8-bit register. Writing any value to this register
clears the Timer3 interrupt in normal mode or resets
a new timeout period in watchdog mode.
Timer3 Load Register
Name
Address
Default Value
Access
T3LD
0xFFFF0360
0x03D7
R/W
This 16-bit MMR holds the Timer3 reload value.
Timer3 Value Register
Name
Address
Default Value
Access
T3VAL
0xFFFF0364
0x03D7
R
This 16-bit, read-only MMR holds the current Timer3 count value.
Timer3 Clear Register
Name
Address
Default Value
Access
T3ICLR
0xFFFF036C
0x00
W
This 8-bit, write-only MMR is written (with any value) by user
code to refresh (reload) Timer3 in watchdog mode to prevent a
watchdog timer reset event.
Timer3 Control Register
Name
Address
Default Value
Access
T3CON
0xFFFF0368
0x00
R/W
once
only
The 16-bit MMR configures the mode of operation of Timer3.
as described in detail in Table 115.
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