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參數(shù)資料
| 型號(hào)： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 72/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲(chǔ)器容量： | 126KB（63K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 74 of 92
The Timer0 interface consists of six MMRs, shown in Table 108.
Table 108. Timer0 Interface MMRs
Name
Description
T0LD
A 16-bit register that holds the 16-bit value loaded
into the counter. Available only in 16-bit mode.
T0CAP
A 16-bit register that holds the 16-bit value captured
by an enabled IRQ event. Available only in 16-bit mode.
T0VAL0/
T0VAL1
TOVAL0 is a 16 bit register that holds the 16 least
significant bits (LSBs).
T0VAL1 is a 32-bit register that holds the 32 most
significant bits (MSBs).
T0VAL0 and T0VAL1 are read only. In 16-bit mode, 16-
bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0
and 32-bit T0VAL1 are used.
T0ICLR
An 8-bit register. Writing any value to this register
clears the interrupt. Available only in 16-bit mode.
T0CON
The configuration MMR (see Table 109).
TIMER0IRQ
CORE CLOCK
FREQUENCY
CAPTURE
IRQ[31:0]
16-BIT LOAD
48-BIT
UP COUNTER
16-BIT
UP/DOWN COUNTER
TIMER0 VALUE
PRESCALER 1,
16, 256, OR 32768
06
02
0-
05
0
Figure 55. Timer0 Block Diagram
Timer0 Value Register
Name
Address
Default Value
Access
T0VAL0
0xFFFF0304
0x00
R
T0VAL1
0xFFFF0308
0x00
R
T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold
the 16 least significant bits and 32 most significant bits,
respectively. T0VAL0 and T0VAL1 are read-only. In 16-bit
mode, 16-bit T0VAL0 is used. In 48-bit mode, both 16-bit
T0VAL0 and 32-bit T0VAL1 are used.
Timer0 Capture Register
Name
Address
Default Value
Access
T0CAP
0xFFFF0314
0x00
R
This is a 16-bit register that holds the 16-bit value captured by
an enabled IRQ event; available only in 16-bit mode.
Timer0 Control Register
Name
Address
Default Value
Access
T0CON
0xFFFF030C
0x00
R/W
The 17-bit MMR configures the mode of operation of Timer0.
Table 109. T0CON MMR Bit Designations
Bit
Value
Description
31:18
Reserved.
17
Event Select Bit.
Set by user to enable time capture of an
event.
Cleared by user to disable time capture of
an event.
16:12
Event Select Range, 0 to 31. The events are as
described in the Timers section.
11
Reserved.
10:9
Reserved.
8
Count Up. Available only in 16-bit mode.
Set by user for timer 0 to count up.
Cleared by user for timer 0 to count down
(default).
7
Timer0 Enable Bit.
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
6
Timer0 Mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free-running
mode (default).
5
Reserved.
Timer0 Mode of Operation.
0
16-bit operation (default).
4
1
48-bit operation.
Prescaler.
0000
Source clock/1 (default).
0100
Source clock/16.
1000
Source clock/256.
3:0
1111
Source clock/32,768.
Timer0 Load Register
Name
Address
Default Value
Access
T0LD
0xFFFF0300
0x00
R/W
T0LD is a 16-bit register that holds the 16-bit value that is
loaded into the counter; available only in 16-bit mode.
Timer0 Clear Register
Name
Address
Default Value
Access
T0ICLR
0xFFFF0310
0x00
W
This 8-bit, write-only MMR is written (with any value) by user
code to refresh (reload) Timer0.
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